Hi,

I would like to benchmark my ADC. I can calculate a sensitivity value based on the information in the datasheet. However, I would like to measure/benchmark this figure. Is there a standard method for doing this? How would you go about measuring accuracy of any ADC. Considering these a 24bit chip can measure down to few uV it is not very straight forward to plug in a signal gen to the inputs.

Would high ratios of voltage divider help to generate a low noise low voltage signal in uV range to feed into the ADC?

Wouldn't Johnson noise stop one from using high value resister in this case?

 

Hi,

I would like to benchmark my ADC. I can calculate a sensitivity value based on the information in the datasheet. However, I would like to measure/benchmark this figure. Is there a standard method for doing this? How would you go about measuring accuracy of any ADC. Considering these a 24bit chip can measure down to few uV it is not very straight forward to plug in a signal gen to the inputs.

Would high ratios of voltage divider help to generate a low noise low voltage signal in uV range to feed into the ADC?

Wouldn't Johnson noise stop one from using high value resister in this case?

First, you mention "sensitivity", then "accuracy", followed by what I interpret as "resolution", and, finally, noise.

Aside from "sensitivity" (a term I do not recognize wrt a/d converters), all these parameters are stated in the datasheet.

You want to confirm these? You need to measure them by using their test circuits that are usually detailed in the datasheet. Often, you can purchase an evaluation board designed by the chip manufacturer. But your instrumentation must have better specifications than the part you are testing -- or all bets are off. The mfgrs. spend lots of money on their test equipment. Most of us don't.

Regarding Johnson noise, this is easily quantifiable. And its contribution adds (in RMS fashion) to the converter noise (and, likely, the reference noise as well). Add up your noise sources: this represents the best noise performance you can expect.

Hi-res ΔΣ converters usually have more noise than bits (albeit very low). Histograms are usually provided showing a bell-curve of the expected codes vs. input voltage. This is useful information -- it tells you the uncertainty of any instantaneous conversion (and therefore the real resolution or ENOB). If it is not good enough, you have the opportunity to trade time for better resolution. You do this via digital filtering -- FIR or IIR. I prefer a boxcar FIR followed by a single or 2 order IIR.

Here is a thread of mine where I achieve 55nVp-p of noise over a one minute measurement interval using a TI ADS1242.

Hope this helps.

 

I would like to benchmark my ADC.

There are several figures of merit that you can measure, though with a 24-bit ADC you have the significant challenge of creating a test circuit that can measure 24 noise-free bits. For example, the LSB on a 24-bit single-ended ADC with 5V vref is about 298 nV, which means that you'd need a test circuit + environment whose noisefloor is lower than 298 nV for many of the tests. Considering that the rms Johnson noise of a 1k resistor over a 20 kHz bandwidth is almost double that, you can imagine the difficulty of such tests. Often the manufacturer will sell an evaluation board with the reference design, getting you halfway there.

This chapter from Analog's excellent Data Conversion Handbook should help you get some ideas: https://www.analog.com/media/en/tra...ndbooks/Data-Conversion-Handbook/Chapter5.pdf

But for a quick and dirty test of your working noisefloor, feed your ADC a dc voltage of half the vref and plot the output codes. Do this at progressively larger resolutions, i.e., start with the ADC in 12-bit mode, then 16-, then -18, then -24, noting when the LSB starts jumping around. This will almost certainly be noise from your voltage source + circuit + environment and not from your ADC, but it will show you much work you have to do to get a 24 noise-free bits.

Incidentally, sensitivity is not a term usually associated with ADCs. The PDF above should get you up to speed on the figures of merit.

 

I do realize that my post was all over the place. It is just that if a sensitivity figure is to be reported for a measurement device how would one go about benchmarking it. A value can be calculated based on the information in the datasheet, but what is the best method for testing that?

 

It is just that if a sensitivity figure is to be reported for a measurement device how would one go about benchmarking it?

You start by defining "sensitivity" with respect to the measuring device in question.

 

There are several figures of merit that you can measure, though with a 24-bit ADC you have the significant challenge of creating a test circuit that can measure 24 noise-free bits. For example, the LSB on a 24-bit single-ended ADC with 5V vref is about 298 nV, which means that you'd need a test circuit + environment whose noisefloor is lower than 298 nV for many of the tests. Considering that the rms Johnson noise of a 1k resistor over a 20 kHz bandwidth is almost double that, you can imagine the difficulty of such tests. Often the manufacturer will sell an evaluation board with the reference design, getting you halfway there.

This chapter from Analog's excellent Data Conversion Handbook should help you get some ideas: https://www.analog.com/media/en/tra...ndbooks/Data-Conversion-Handbook/Chapter5.pdf

But for a quick and dirty test of your working noisefloor, feed your ADC a dc voltage of half the vref and plot the output codes. Do this at progressively larger resolutions, i.e., start with the ADC in 12-bit mode, then 16-, then -18, then -24, noting when the LSB starts jumping around. This will almost certainly be noise from your voltage source + circuit + environment and not from your ADC, but it will show you much work you have to do to get a 24 noise-free bits.

Incidentally, sensitivity is not a term usually associated with ADCs. The PDF above should get you up to speed on the figures of merit.

Thank you