So I am in a VHDL class, and I stuck on this problem.
The instructor has asked us to design a 2:4 decoder using 2x1 MUX.
Obviously, I would be needing at least 4 of these multiplexers to generate 4 outputs of the decoder.
Someone please guide me to design this decoder.
Thank you.
The instructor has asked us to design a 2:4 decoder using 2x1 MUX.
Obviously, I would be needing at least 4 of these multiplexers to generate 4 outputs of the decoder.
Someone please guide me to design this decoder.
Thank you.