A 2:4 decoder homework problem

Thread Starter

freak101

Joined Aug 7, 2017
37
So I am in a VHDL class, and I stuck on this problem.
The instructor has asked us to design a 2:4 decoder using 2x1 MUX.
Obviously, I would be needing at least 4 of these multiplexers to generate 4 outputs of the decoder.
Someone please guide me to design this decoder.

Thank you.
 

WBahn

Joined Mar 31, 2012
24,691
That's not how homework help works. You need to show your best attempt to work your homework. We will then try to help you discover the problem you are having so that you can get past it. That way you own the solution.

You might start be simplifying the problem -- can you make a 1:2 decoder using 2:1 MUXes?
 

WBahn

Joined Mar 31, 2012
24,691
@WBhan

Is that a correct implementation of 1:2 decoder?
It'll perform the correct function, but is it made entirely from 2:1 MUXes? What purpose do the two MUXes you do have serve? Seems like you could just eliminate them - unless you are using them as buffers.

The idea is to make something that is easily expandable to more bits.

It might make more sense to you to jump straight to the next step, which is to make a 1:2 decoder with an enable input (all outputs are LO unless the enable is HI) using just two 2:1 MUXes.
 

Thread Starter

freak101

Joined Aug 7, 2017
37
It'll perform the correct function, but is it made entirely from 2:1 MUXes? What purpose do the two MUXes you do have serve? Seems like you could just eliminate them - unless you are using them as buffers.
Since my instructor asked me to use mux to implement a decoder, I did that. Is there any other better way?
 

Thread Starter

freak101

Joined Aug 7, 2017
37
It might make more sense to you to jump straight to the next step, which is to make a 1:2 decoder with an enable input (all outputs are LO unless the enable is HI) using just two 2:1 MUXes.
How about this?
 

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