I'm new to digital design, teaching myself through AI and books ('Digital Logic and Computer Design' & 'Computer Structures: Readings and Examples'). Progress is slow, and I constantly ask myself, "Am I doing this right?" As you can imagine, it's a little nerve-wracking at times; fortunately, I've broken down my project (a 6-bit microprocessor) into chunks in order to not get overwhelmed.

The attached circuit is a 6-bit register, and what I'd like is a critique. Is it understandable? I mean, it's clear to me and the sim but that's a limited audience.

The circuit can be described as follows:
• Z{n} ← 【~RST ≡ 0】 » ↑clk ? ~RST
• Z{n} ← 【M_en ≡ 1】 » ↑clk ? D_in{5:0}
• D_out{5:0} ← 【R/~W ≡ 0】 ? Z{n}

..to translate from my shorthand (heh):
• if ~RST signal is low, on the next rising clock D flip-flop Z{n} then loads ~RST
• if M_en signal is high, on the next rising clock D flip-flop Z{n} then loads bus D_in{5:0}
• if R/~W signal is low, bus D_out{5:0} then loads Z{n}

 

The circuit is very well drawn, and fairly easy to follow.
But it must be toolate in the day for me to evaluate the functionality. Of course, with shift registers I have always cheated and used the wonderful data sheets published. The truth tablesand timing charts are rather useful.

 

I'm new to digital design, teaching myself through AI and books ('Digital Logic and Computer Design' & 'Computer Structures: Readings and Examples'). Progress is slow, and I constantly ask myself, "Am I doing this right?" As you can imagine, it's a little nerve-wracking at times; fortunately, I've broken down my project (a 6-bit microprocessor) into chunks in order to not get overwhelmed.

The attached circuit is a 6-bit register, and what I'd like is a critique. Is it understandable? I mean, it's clear to me and the sim but that's a limited audience.

The circuit can be described as follows:
• Z{n} ← 【~RST ≡ 0】 » ↑clk ? ~RST
• Z{n} ← 【M_en ≡ 1】 » ↑clk ? D_in{5:0}
• D_out{5:0} ← 【R/~W ≡ 0】 ? Z{n}

..to translate from my shorthand (heh):
• if ~RST signal is low, on the next rising clock D flip-flop Z{n} then loads ~RST
• if M_en signal is high, on the next rising clock D flip-flop Z{n} then loads bus D_in{5:0}
• if R/~W signal is low, bus D_out{5:0} then loads Z{n}

I would have laid out the diagram a bit differently, but your layout is clean and consistently organized.

The one thing that I might push back on is the naming of the R/W signal. This would normally mean "Read, Not Write", but (at least at the level of this diagram), it looks more like an active-LO output enable.

So consider what "read" and "write" mean as far as this register is concerned and perhaps pick a different name accordingly.

 

The circuit is very well drawn, and fairly easy to follow.
But it must be toolate in the day for me to evaluate the functionality. Of course, with shift registers I have always cheated and used the wonderful data sheets published. The truth tablesand timing charts are rather useful.

Ha, I appreciate that! I admit I started this whole project in a very backwards manner, first in sim (without anything other than a very, very basic idea of digital logic: 'I know what gates do! yay!'), and it is only now as I dive deeper into the subject that I am learning about everything else—this is how one ends up with their own "notation" (and other oddities).

The one thing that I might push back on is the naming of the R/W signal. This would normally mean "Read, Not Write", but (at least at the level of this diagram), it looks more like an active-LO output enable.

I think the proper name for the signal would be more like "EO" (or "OE"?), right? I don't quite remember how I ended up with R/W, but I haven't really been confident in it. I believe I had it as '~W' originally, but that didn't seem right. As you implied.. I'm not writing anything, it's just an output. (this discovery of the "EO" label was within the past few days.. quite embarassing, really.

 

I think the proper name for the signal would be more like "EO" (or "OE"?), right? I don't quite remember how I ended up with R/W, but I haven't really been confident in it. I believe I had it as '~W' originally, but that didn't seem right. As you implied.. I'm not writing anything, it's just an output. (this discovery of the "EO" label was within the past few days.. quite embarassing, really.

A name such as /OE (Not Output Enable) would be very typical for this functionality.