I have a single data pulse on the SER. I need that pulse to shift sequentially to each output pin (Q0-Q7).

I thought about the SRCLK AND RCLK requirements.

If I was to delay the SER pulse by using 2 inverters, I could use that delayed pulse as the SRCLK, which would then shift the data into the chips shift register.

Then also use that delayed pulse and delay it again as the RCLK, which would then transfer the data from the chips shift register onto the output pins.

What I cannot find out is if this is feasible and practicable and whether there is enough delay in the pulses (I think propagation time).

Not found any 'typical circuits' on the internet that show anybody doing this.



The next 7 data pulses are all '0' . So all I should see is a single logic '1' going from Q0 to Q7, with the next clock pulse pushing that off the end, and setting them all to logic '0'

Is this right in my understanding, or is there a better way, or do I need a longer delay, and how ?

 

I have a single data pulse on the SER. I need that pulse to shift sequentially to each output pin (Q0-Q7).

It is not clear what you mean by a “single data pulse”.

Can you show the difference between a “0” pulse and a “1” pulse by using drawings?

 

Must you use the 595? If you don't need the output latches, you would be better off with a 74HC164.
Although, you seem to be trying to achieve what is very easily done by a 4017.

 

What you are proposing has been done before and should work. Here's an illustration using RC delays rather than propagation delay.

https://www.romanblack.com/shift1.htm

Or here - https://nerdralph.blogspot.com/2018/06/fast-1-wire-shift-register-control.html

Plenty of examples on the web.

 

It is not clear what you mean by a “single data pulse”.

Can you show the difference between a “0” pulse and a “1” pulse by using drawings?

I hope you can understand my logic drawing.



The pulses within each period, will be of different widths. To get the SER data, I am only sensing the rising edge of each pulse ie there is data there, not interested in the width. The next SER data is again by sensing the rising ....... The clock will always be related to the rising edge of each pulse, and not an oscillator clock signal.

I hope you are still with me.

 

I hope you can understand my logic drawing.

View attachment 355100

The pulses within each period, will be of different widths. To get the SER data, I am only sensing the rising edge of each pulse ie there is data there, not interested in the width. The next SER data is again by sensing the rising ....... The clock will always be related to the rising edge of each pulse, and not an oscillator clock signal.

I hope you are still with me.

Still looks to me like what a 4017 does.

 

I have a single data pulse on the SER. I need that pulse to shift sequentially to each output pin (Q0-Q7).

I thought about the SRCLK AND RCLK requirements.

If I was to delay the SER pulse by using 2 inverters, I could use that delayed pulse as the SRCLK, which would then shift the data into the chips shift register.

Then also use that delayed pulse and delay it again as the RCLK, which would then transfer the data from the chips shift register onto the output pins.

What I cannot find out is if this is feasible and practicable and whether there is enough delay in the pulses (I think propagation time).

Not found any 'typical circuits' on the internet that show anybody doing this.

View attachment 355097

The next 7 data pulses are all '0' . So all I should see is a single logic '1' going from Q0 to Q7, with the next clock pulse pushing that off the end, and setting them all to logic '0'

Is this right in my understanding, or is there a better way, or do I need a longer delay, and how ?

That won't work, because if your next 7 data pulses are all "0", the level doesn't change, and there is never going to be any SRCLK pulses derived to clock the register in the first place! The data pin has to be separate from the other two, whereas RCLK could be a delayed version of SRCLK.

 

What you are proposing has been done before and should work. Here's an illustration using RC delays rather than propagation delay.

https://www.romanblack.com/shift1.htm

Or here - https://nerdralph.blogspot.com/2018/06/fast-1-wire-shift-register-control.html

Plenty of examples on the web.

I like the look of https://nerdralph.blogspot.com/2018/06/fast-1-wire-shift-register-control.html

 

I am beginning to think that CD4022 would be a more ideal choice than a 74HC595.

The benefits from my initial checking out of the data sheets, is that it can operate from 12v DC. This would reduce the component count, as I would not need a buck power supply 12v to 5v. Just need to mod optoisolator and IRLZ44 circuits.

Any thoughts or preferences between the 2 chips ?

 

I am beginning to think that CD4022 would be a more ideal choice than a 74HC595.

The benefits from my initial checking out of the data sheets, is that it can operate from 12v DC. This would reduce the component count, as I would not need a buck power supply 12v to 5v. Just need to mod optoisolator and IRLZ44 circuits.

Any thoughts or preferences between the 2 chips ?

A 4022 is a 4017 with only 8 output. I've been saying all along that you need a counter not a shift register.

 

instead of describing how you want to accomplish it, please share what is it that you are trying to accomplish.
all i see is that you have single GPIO and you want it to control several outputs. some posts have already addressed that. CD4017 and CD4022 have 1-of-N output. solutions using shift register allow you to have any output (several bits set).

 

I hope you can understand my logic drawing.

I am sorry. I still do not understand what is the problem.
As panic says, do not describe your plans for solving the problem. First, we need to know what is the problem.
I still do not know what is a "single data pulse". A pulse is a pulse. The only thing that can change is the width of the pulse, assuming the pulse height stays the same.



Perhaps other members have a better understanding and can explain it to me.

 

Perhaps other members have a better understanding and can explain it to me.

I think that "I have a single data pulse on the SER. I need that pulse to shift sequentially to each output pin (Q0-Q7)." means he wants a circuit with 8 outputs where they go high in turn on the clock pulse (like a 4017/4022 does)

 

I think that "I have a single data pulse on the SER. I need that pulse to shift sequentially to each output pin (Q0-Q7)." means he wants a circuit with 8 outputs where they go high in turn on the clock pulse (like a 4017/4022 does)

Thanks @Ian0
What determines when to start at Q0?

 

I think that "I have a single data pulse on the SER. I need that pulse to shift sequentially to each output pin (Q0-Q7)." means he wants a circuit with 8 outputs where they go high in turn on the clock pulse (like a 4017/4022 does)

Thanks for being persistent with me. But yes, 4022 is looking good, as its 8 bit. I am working on this.

But I must take note of the message by sarahmcml that re the clock timing and investigate further.

 

Thanks for being persistent with me. But yes, 4022 is looking good, as its 8 bit. I am working on this.

But I must take note of the message by sarahmcml that re the clock timing and investigate further.

@sarahMCML 's comments refer to the data inputs of a shift register.

 

Thanks for being persistent with me. But yes, 4022 is looking good, as its 8 bit. I am working on this.

But I must take note of the message by sarahmcml that re the clock timing and investigate further.

you still qualify things as "good" rather than explaining what you have and what outcome you want.