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I'm new to digital design, teaching myself through AI and books ('Digital Logic and Computer Design' & 'Computer Structures: Readings and Examples'). Progress is slow, and I constantly ask myself, "Am I doing this right?" As you can imagine, it's a little nerve-wracking at times; fortunately...

I have a single data pulse on the SER. I need that pulse to shift sequentially to each output pin (Q0-Q7). I thought about the SRCLK AND RCLK requirements. If I was to delay the SER pulse by using 2 inverters, I could use that delayed pulse as the SRCLK, which would then shift the data into...