In order to aid you, would it be possible for you to share such a logic diagram.COUNTER AND ASYNCHRONOUS RESET
as I expressed in the title i need to write verilog code for that circut without using if else staments so I need to understand logic diagram
Sir this is the all I have I was looking for a logic diagram so that i can write a code but if there is a code that already written I could go with that aswellIn order to aid you, would it be possible for you to share such a logic diagram.
Side Note: there is a huge difference between a counter and a parallel load shift register. What is you are actually trying to write code for?
Im working on them sirThat clears up the first mystery. You want two devices in one package. The usual method of problem solution is called "divide and conquer". If we break the problem into two subproblems:
Can you design those things separately?
- A Parallel Load Shift Register
- A 4-synchronous counter
shifter is done but Im sturggiling in counter thanks for your help ^^I'm not familiar with Verilog, or VHDL for that matter, and I don't know how to help you with that part. If you are looking for functional logic diagrams you can go to actual datasheets for those parts.
For the synchronous 4-bit counter you could look at: SN54HC161, SN74HC161 datasheet (Rev. D) (ti.com) see page 3.
For the parallel load shift register you could look at: SNx4HC165 8-Bit Parallel-Load Shift Registers datasheet (Rev. H) (ti.com) see page 1.
Thanks in advance ^^Some additional hints:
The solutions to this problem are not unique and you have a good deal of flexibility. Don't worry about finding an optimal solution at this time. Just make it work.
- Serial input to the least significant bit should be set to logic 0.
- Loading the Shift Register and "Clearing/Presetting" the Counter should happen on the same clock edge
- The counter can start and end at any convenient pair of values whose difference is 8.
- The counter should hold or increment based on the most significant bit of the shift register, on the clock edge following the removal of the LOAD_ENABLE signal.
- The counter can be disabled when the shift register contains all zeros
sir we designed them seperatlyThat clears up the first mystery. You want two devices in one package. The usual method of problem solution is called "divide and conquer". If we break the problem into two subproblems:
Can you design those things separately?
- A Parallel Load Shift Register
- A 4-synchronous counter
That's good.sir we designed them seperatly