Hi,



See this snap shot this was video lecture recorded by instructor but he did not explain this right shift register timing diagram well. Please explain it, how this diagram works ?

Thanks.

 

What is it that you are having trouble with in regards to the diagram?

At the rising edge of the clock, Q_n takes on the value that Q_(n-1) had prior to the clock edge, except for Q_0 which takes on the value of the Data input.

 

I got your point,

Thanks

 

But I have one more question:

Practically where we use 4-bit right shift register ?

 

hi,
Check this link.
http://www.allaboutcircuits.com/textbook/digital/chpt-12/introduction-to-shift-registers/
E

 

hi,

Thanks, this helped me