It certainly looks to me like the latch and reset pulses will be within a very few NANOSeconds of each other. so of course it will not work. the reset must not start until after the latch command has terminated. That is because the CD4042 is a STATE controlled device, not an edge triggered device. So the latch pulse must end before the reset pulse starts.
READING AND UNDERSTANDING the description of how the IC actually functions is often rather useful.

 

It certainly looks to me like the latch and reset pulses will be within a very few NANOSeconds of each other. so of course it will not work. the reset must not start until after the latch command has terminated. That is because the CD4042 is a STATE controlled device, not an edge triggered device. So the latch pulse must end before the reset pulse starts.
READING AND UNDERSTANDING the description of how the IC actually functions is often rather useful.

If you know how to fix the circuit then please share.

 

TS needs to verify the pulses using the oscilloscope. TS needs to stop thinking about how to get the circuit to work.
Firstly, verify that the first differentiator is working by examining the output of capacitor C1.
If the pulse height is too low, TS needs to increase the value of the capacitor or the value of the resistor.
Next, examine the pulse output as reshaped by the NAND gate.

 

TS needs to verify the pulses using the oscilloscope. TS needs to stop thinking about how to get the circuit to work.
Firstly, verify that the first differentiator is working by examining the output of capacitor C1.
If the pulse height is too low, TS needs to increase the value of the capacitor or the value of the resistor.
Next, examine the pulse output as reshaped by the NAND gate.

Attached is scope image of C1 output and U1 output and U2 output.
Channel 1 => 1 Hz Timebase
Channel 2 => C1 output => pulse is generated
Channel 3 => U1 output => pulse is shaped
Channel 4 => U2 output => pulse inverted (STORE)

Scope image of C2 and U3 output.
Channel 1 => 1 Hz Timebase
Channel 2 => C2 output => pulse is generated
Channel 3 => U3 output => pulse is shaped (RESET)

We haven't discussed the pulse height before but it appears to be 5 volts or very close to it.

 

The pulses look good, but a bit wide at 20 ms. We will attempt to reduce this later.

Now you want to generate another pulse on the trailing edge of this pulse.
If you use the rising edge, you want R3 to be a pull-down resistor.
If you use the falling edge, you want R3 to be a pull-up resistor.

 

The pulses look good, but a bit wide at 20 ms. We will attempt to reduce this later.

Now you want to generate another pulse on the trailing edge of this pulse.
If you use the rising edge, you want R3 to be a pull-down resistor.
If you use the falling edge, you want R3 to be a pull-up resistor.

Sorry. I am to generate another pulse on the trailing edge of what pulse?

 

the entire thread was talking about three steps in operation of the circuit : counting (enable counter), storing (latch value), and resetting counter. normally one would generate control signal for each. but in your case controls are simplified to the most basic form, where output of the timebase is used directly as "counter enable". the remaining two signals are the ones you are trying to create.... STORE and RESET.

several people chimed in and offered comments but there is a lot of voices and things can get confusing. nobody is bringing up Enable signals any more so you only need to deal with the two - STORE and RESET. clear now?

you can choose what you want to do but it is not a bad idea to pick one voice and follow it. so far MrChips is the one spending most time working with you and trying to guide you step by step.

if you are going to work with him, then follow his suggestions and do it with him - as directed. if you want to learn, do not try to lead and mix in too many observations, just do what you are asked to do.

he was asking you to do ONE control signal (STORE) and confirm results. but you went ahead and involved report on all three gates which only makes this process harder.

so first image in post #64 is what he is talking about (STORE signal). that is the "first" signal (STORE) of two signals you need to create.

then he asked you to make another monostable that is triggered by the "first" signal. this way RESET would occur later... after STORE signal...
your second image shows that reset waveforms are NOT triggered by STORE signals. you are STILL trying to generate RESET that is triggered by timebase signal so the RESET pulse timing is off...

 

If you know how to fix the circuit then please share.

I DID SHARE the scheme back in post #44, and it seems that none were interested in even acknowledging my suggestion. And still, the last circuit posted is still based on the theory that the CD4042 is edge triggered, which is not the case.
I have designed a lot of counters over the years, and very early I learned that RC timers were not a good choice. So why not use a scheme that allows a complete analysis of how it works without needing any edge triggered timers to create the three or four required commands, which I also explained back a ways.

I also explained the four actions that need to happen for each measuring period. Evidently nobody noticed that. Certainly the scheme that has failed to work so far is simpler, but how useful is a counter that does ot work???

AND, consider that if your timer collection triggers the reset before the save sequence is completed, there is no predicting what will be saved. THAT is why closing the count gate prior to latching the data is a good idea, especially since you are using a ripple counter.

 

I am sure that the TS has heard the proverb about the man and the fish. This same story applies here.
I can give you the design. Or I can teach you how to do the design yourself.

We cannot keep on just giving you the answers. You have to learn how to figure out things on your own.

Your goal is to design a frequency counter.
Your current task is to generate two pulses, a STORE pulse followed by a RESET pulse.
We have given you the methods and you have the equipment to test and verify this.
Now it is up to you.

 

I am sure that the TS has heard the proverb about the man and the fish. This same story applies here.
I can give you the design. Or I can teach you how to do the design yourself.

We cannot keep on just giving you the answers. You have to learn how to figure out things on your own.

Your goal is to design a frequency counter.
Your current task is to generate two pulses, a STORE pulse followed by a RESET pulse.
We have given you the methods and you have the equipment to test and verify this.
Now it is up to you.

Why all of a sudden are you talking like this?

I sent you a schematic and in post #64 I posted the scope images and you said the
pulses looked good and they were 20 ms but we would take care of the width later.
You then told me to generate another pulse. I thought we only needed two pulses.
Now you tell me to get lost. Why?

 

I explained the reason for multiple control signals in quite a bit of detail already. That was in post #44

 

Why all of a sudden are you talking like this?

I sent you a schematic and in post #64 I posted the scope images and you said the
pulses looked good and they were 20 ms but we would take care of the width later.
You then told me to generate another pulse. I thought we only needed two pulses.
Now you tell me to get lost. Why?

You need to generate two pulses, one followed by another, not three pulses.
Your oscilloscope is showing two pulses occurring at the same time. I have given you all the information you need to make one pulse followed by another. Can you figure this out by yourself?

 

Here are two very similar circuits that form the derivative of the input signal.
Study each circuit carefully and draw the input and output waveforms for each circuit.



Do not proceed until you fully understand the operation and role that these two circuits play in your current design.

 

You need to generate two pulses, one followed by another, not three pulses.
Your oscilloscope is showing two pulses occurring at the same time. I have given you all the information you need to make one pulse followed by another. Can you figure this out by yourself?

WRONG!!!! An accurate counter needs four commands, at least: First command is "STOP COUNTING", meaning the counter enable switches off. Then, after the last count has had time to ripple thru the string, the second command is LATCH DATA. With the CD4042, which is not edge triggered, that pulse must end before the reset pulse starts. Then the third pulse is "COUNTER RESET", and the fourth command is "Start Counting", which means the counter enable switches back on. For the greatest accuracy the start counting, or the counter reset command also resets the time base counter string so that every time base period is exactly the same.
Generating that whole set of commands correctly by means of RC time delays is rather tricky, and that is why using the CD4017 and a CD4013 is a better scheme.
Back in 1972, when logic ICs were more expensive, the RC timer chips made a bit of sense, but not today.
What scheme is the TS using to produce the time base? If the time base uses an oscillator and divider string then the faster frequency to step the 4017 is conveniently available.

 

Here are two very similar circuits that form the derivative of the input signal.
Study each circuit carefully and draw the input and output waveforms for each circuit.

Do not proceed until you fully understand the operation and role that these two circuits play in your current design.

I built these 2 circuits using 0.1 uF caps and 2.2K resistors. The input signal is a 1 Hz square wave.
These are both differentiator circuits. Each cycle of the square wave input waveform produces two spikes at the output, one positive and one negative and whose amplitude is equal to that of the input, ie. ≈ 5 volts. t = R * C = 220 usec

 

I built these 2 circuits using 0.1 uF caps and 2.2K resistors. The input signal is a 1 Hz square wave.
These are both differentiator circuits. Each cycle of the square wave input waveform produces two spikes at the output, one positive and one negative and whose amplitude is equal to that of the input, ie. ≈ 5 volts. t = R * C = 220 usec

We can see the spikes. Now you need to expand the horizontal scale so that the time, voltage, and shape of the spike is clearly visible.

 

We can see the spikes. Now you need to expand the horizontal scale so that the time, voltage, and shape of the spike is clearly visible.

Expanded time scale illustrating spikes.

 

MrChips gave you the idea in post #73. If you put inverters in the correct places you will get the proper pulse train. I have it working here!

 

Expanded time scale illustrating spikes.

Can you explain in words what you are seeing on the oscilloscope with respect to the shape and voltages of the spikes in the two separate circuits? In other words, what is the cause of the shape and voltages observed on the oscilloscope?

Hint: The results are different. What is the difference between the two results?

 

Can you explain in words what you are seeing on the oscilloscope with respect to the shape and voltages of the spikes in the two separate circuits? In other words, what is the cause of the shape and voltages observed on the oscilloscope?

Hint: The results are different. What is the difference between the two results?

View attachment 335895

It appears that channel 2 is riding on zero volts and channel 3 is riding on + 5 volts.