good day to you!
I am trying to bias a junction field effect transistor (2N4117) as a common drain circuit (audio) with gain ~1 by using only 2 resistors and a controllable voltage source like in this picture:
http://www.piclist.com/images/ca/ualberta/phys/www/http/~gingrich/phys395/notes/img659.gif
The 2N4117 has a threshold voltage of ~ -1V and Idss of 0.03 mA to 0.09 mA.
My AC input voltage will swing around +/-3V and so should the output (of course the gain can never reach 1 but approx.).
Is this even possible in practice? Spice tells me I need an Rs of insane 100 Mega Ohms to achive this. My hand calculations say a way lower Rs in the kOhms region is okay to bias the output at 3 V.
I imagine usually the way of biasing with one device is like in an A-class amplifier where
Vout @ Q-point >> vout_AC swing
But can I do it like that, considering the JFET also conducts at negative Vgs?
I got a little bit confused here maybe somebody can bring me back on the right track thanks a bunch!

 

Something like this?

If the source resistor value is less than about 1/10 of the bias resistor value, distortion becomes noticeable.

 

Something like this?
View attachment 107108
If the source resistor value is less than about 1/10 of the bias resistor value, distortion becomes noticeable.

thanks for the reply!
Yeah basically the same! Only difference is that I do not have access to the Gate electrode. It is fixed to AGND with 1 MOhm like in your circuit.... so it is the same just without the Bias DC voltage you have.

 

I do not have access to the Gate electrode

Then I'm unclear what you're trying to do. How do you apply the input signal? Are you using Vdd as the signal input? What does your "controllable voltage source" do?

 

Then I'm unclear what you're trying to do. How do you apply the input signal? Are you using Vdd as the signal input? What does your "controllable voltage source" do?

thanks for taking the time Alec_t! It is a sensor which has the transistor inside where the three electrodes come out... Drain, source and GND (which is internally connected to the gate via a huge resistor like in the picture I posted above).
I now want to get a source follower by just inserting a resistor Rs between source and GND. The V+ is connected to the voltage source which is not critical here so I chose 10 V.
Spice tells me 100Mega Ohms as Rs but then the Ids current is so low that I have doubt it works in practice

 

The problem here is that you're trying to swing the source by +/- 3 volts. For that to happen, the source resistor must drop at least 3 volts and at that point, you're so deep in cutoff that the current isn't even on the charts. The only way you're going to get this to swing a 6 volt signal is to provide both a positive and a negative supply voltage. Try +/- 15 volts for your model and the mechanism will become clear to you.

 

If I've understood you correctly then, with a 10V supply for Vdd and a 1meg resistor from gate to ground, adding a 680k pull-up from gate to Vdd should do the job, like this:-

 

The problem here is that you're trying to swing the source by +/- 3 volts. For that to happen, the source resistor must drop at least 3 volts and at that point, you're so deep in cutoff that the current isn't even on the charts. The only way you're going to get this to swing a 6 volt signal is to provide both a positive and a negative supply voltage. Try +/- 15 volts for your model and the mechanism will become clear to you.

Thank you guys..
I have now understood the priciple of the negative voltage that is put in the source path and sets a DC bias for the Vgs. Unfortunately I don't have a negative supply voltage and I hear it is not easy building one quickly without experience with it.

 

If I've understood you correctly then, with a 10V supply for Vdd and a 1meg resistor from gate to ground, adding a 680k pull-up from gate to Vdd should do the job, like this:-
View attachment 107142

thanks for the post.
Unfortunately I do not have access to the Gate of the transistor because it is inside the housing of the sensor. Only Drain, Source terminals are available .... the gate is prewired to GND via huge resistor.
This really turned out quite complicated although it seemed so simple
If I had a current source that could supply an Ids of say Ids =Idss, would then the Vgs adapt to being 0V in the Q-point or would the Vgs become negative according to Vgs= -Ids*Rs?
I feel quite lost now

 

I hear it is not easy building one quickly without experience with it.

I don't think so. Try 2 isolated output wall warts and connect them in series, or
Take a simple transformer to make a positive supply and install the diodes and capacitors backwards.
You're not going to need a lot of filtering to keep it smooth at 90 ua.
and, no, don't try to force IDss. The gate won't adapt and you'll let the smoke out.

 

If the gate is inaccessible and is connected to the source via a resistor then the source will be fixed at ~1V above the gate, regardless of which power supplies you use. That will prevent you getting the +-3V swing that you want .

 

If the gate is inaccessible and is connected to the source via a resistor then the source will be fixed at ~1V above the gate, regardless of which power supplies you use. That will prevent you getting the +-3V swing that you want .

I disagree. If the schematic is right and there is no resistor between the source and the connection of the gate resistor, VGs = 0 and IDss is as advertised, 30ua to 90ua.

 

You're right. My bad. LTspice agrees with you too .

 

See

 

You're right. My bad. LTspice agrees with you too .
View attachment 107171

Don't worry. I'm still learning.

 

Don't worry. I'm still learning.

thanks!
at some uA in the Q point I dont even need a regulated negative supply aye?
-5 V as neg. supply is not possible though when Vp is -1V only when Vp is lower

 

Vp is not a factor. You don't run a j-fet at the pinch off voltage because that would mean there is no current! In a source follower circuit, like an emitter follower, the idle current does not change much and therefore, the Vgs (Vbe) does not change much.

Suppose the gate is at zero volts and you provide a -5V supply. Suppose the j-fet idles at 50ua for Vgs = 0
Your source resistor would be 100k to use up 5 volts at 50ua.
As the gate goes to +3v, the voltage at the source becomes a little less than +3v and the current becomes almost 80ua.
This transistor has a transconductance of 140ua/Vgs
The gate becomes 0.214V positive compared to the source, which is not enough to cause current to flow from the gate to the source.
In the other direction, the gate moves to -3v compared to ground and the Vgs becomes -0.214V in order to diminish the normally 50ua current to 20ua.
Your error term would be 0.214v/3v which equals a gain of 0.9287

If you used a -15 volt supply, the source resistor would be 300k to use up 15 volts at 50 ua. The variation in Id would be +/- 10ua to accomplish a change of +/- 3 volts and the variation in Vgs would be +/- 0.0714 volts.
In this case, your gain would be 0.9762

0.07 volts to 0.214 volts is no where near Vp.
Vp is not in the equation.

 

Vp is not a factor. You don't run a j-fet at the pinch off voltage because that would mean there is no current! In a source follower circuit, like an emitter follower, the idle current does not change much and therefore, the Vgs (Vbe) does not change much.

Suppose the gate is at zero volts and you provide a -5V supply. Suppose the j-fet idles at 50ua for Vgs = 0
Your source resistor would be 100k to use up 5 volts at 50ua.
As the gate goes to +3v, the voltage at the source becomes a little less than +3v and the current becomes almost 80ua.
This transistor has a transconductance of 140ua/Vgs
The gate becomes 0.214V positive compared to the source, which is not enough to cause current to flow from the gate to the source.
In the other direction, the gate moves to -3v compared to ground and the Vgs becomes -0.214V in order to diminish the normally 50ua current to 20ua.
Your error term would be 0.214v/3v which equals a gain of 0.9287

If you used a -15 volt supply, the source resistor would be 300k to use up 15 volts at 50 ua. The variation in Id would be +/- 10ua to accomplish a change of +/- 3 volts and the variation in Vgs would be +/- 0.0714 volts.
In this case, your gain would be 0.9762

0.07 volts to 0.214 volts is no where near Vp.
Vp is not in the equation.

thank's for the discussion! Or no discussion... I already had typed a reply but then realized I was wrong after doing some thinking. I was too focused on the Q-point limitation.
But something is still not 100% clear. Normally the current is a function of the Gate-Source voltage in a FET. But here the Gate-Source voltage is itsself a function of the current which is kind of a feedback I guess. You assume that there is a change in the current of 30uA from the idle value when the gate goes to 3V. My way of thinking is the other way round, that I first need to know the gate-source voltage to get the change in the current but I do actually only know the change in the gate voltage. So you say you need a 30uA current-swing at the output to get that 3V to the output and thus 30uA/gm = 0.241V is the change in the gate-source voltage.

 

Yes. The source almost follows the gate and the voltage at the source to -5V resistor almost follows the gate. The "less than one" gain is explained by the transconductance...140 ua/volt of change in Vgs.

here the Gate-Source voltage is itself a function of the current which is kind of a feedback I guess.

This is merely a case of reading the equation differently. If I say E=IR and then I say I=E/R what's the difference? The variables are still locked together with an = sign. Both equations are true. It's just a matter of which variables you start with and which one you want to find.

ps, I don't know what a Q point is.

 

Yes. The source almost follows the gate and the voltage at the source to -5V resistor almost follows the gate. The "less than one" gain is explained by the transconductance...140 ua/volt of change in Vgs.


This is merely a case of reading the equation differently. If I say E=IR and then I say I=E/R what's the difference? The variables are still locked together with an = sign. Both equations are true. It's just a matter of which variables you start with and which one you want to find.

ps, I don't know what a Q point is.

Sorry for the delayed answer. For me the whole transistor is not so intuitive. But once you are in the idle state basically we assume everything is linear and everything is goood and all the problems we had with biasing are already solved.

Btw. the Q just stands for quiescent.