Hello everyone, I’m using Vishay’s Transim tool to design DC-DC converters, and during the initial configuration phase (where you set the minimum and maximum Vin, Iout, frequency, etc.), I’m asked to specify the output current that the DC-DC converter should deliver.

I have therefore drawn up a block diagram of the various integrated circuits that draw current on my future PCB.
The DC-DC converter in question is clearly the block on the left, and I want to know how much output current it will provide (i.e. the sum of the two blue arrows).




1) Correct me if I'm wrong, but I think the output current it will deliver is the sum of all the currents from the 'black' blocks (i.e. not the power NMOS), right?

2) If the answer is yes, in the various datasheets I look at:
2a: the maximum current at their Vdd (maximum current value)
2b: the quiescent current (minimum current value)

3) If I’ve got it right so far and I therefore calculate the maximum current as the sum of all the Imax values across the Vdd pins of the various blocks (the 2a solution) … should I enter a higher value in the simulator? (to allow for a sort of margin)

4) The LDO is linear, so its input current is equal to its output current (which is the sum of the currents from all the modules) + Iquiescent, isn't it?

 

Hello everyone, I’m using Vishay’s Transim tool to design DC-DC converters, and during the initial configuration phase (where you set the minimum and maximum Vin, Iout, frequency, etc.), I’m asked to specify the output current that the DC-DC converter should deliver.

I have therefore drawn up a block diagram of the various integrated circuits that draw current on my future PCB.
The DC-DC converter in question is clearly the block on the left, and I want to know how much output current it will provide (i.e. the sum of the two blue arrows)

1) Correct me if I'm wrong, but I think the output current it will deliver is the sum of all the currents from the 'black' blocks (i.e. not the power NMOS), right?

Yes, but don't forget the transient currents like gate drive which require sufficient local support ie bulk capacitance and then background current to replenish that.You can estimate those by looking at the NMOS total gate charge Qc, switching time ts, and PWM frequency fsw. Crudely, from memory, Iavg = Qc * fsw/ts, per MOSFET.

2) If the answer is yes, in the various datasheets I look at:
2a: the maximum current at their Vdd (maximum current value)
2b: the quiescent current (minimum current value)

2a It's a good start, but many data sheets don't quote max figures.

3) If I’ve got it right so far and I therefore calculate the maximum current as the sum of all the Imax values across the Vdd pins of the various blocks (the 2a solution) … should I enter a higher value in the simulator? (to allow for a sort of margin)

Yes, 10 - 15% is a good margin.

4) The LDO is linear, so its input current is equal to its output current (which is the sum of the currents from all the modules) + Iquiescent, isn't it?

Pretty much.

 

Yes, but don't forget the transient currents like gate drive which require sufficient local support ie bulk capacitance and then background current to replenish that.You can estimate those by looking at the NMOS total gate charge Qc, switching time ts, and PWM frequency fsw. Crudely, from memory, Iavg = Qc * ts * fsw, per MOSFET.

Thank you very much for your reply.

1) I didn’t quite understand your answer regarding the "transient currents like gate drive".
Do you mean the blue arrows (on Vdd) or the orange ones on the nmos gates?
(I'm not referring to the orange wire that indicates the 48V DC bus!)


2) If you mean the orange ones, why should I care about them?
To supply current to the NMOS gate, the ISL78434 driver has to draw it from the blue Vdd line... so I just need to take its maximum value from the datasheet .. am I wrong?



.



I certainly need to take into account the ‘VDD Operating Current’, i.e. the current required to power the chip’s internal logic circuits.
In the datasheet, it is calculated under certain test conditions .. I don’t know what mine will be (I don’t know the duty cycle, I don’t know Rdt, etc.), but let’s assume, for simplicity’s sake, that they are the same as in the datasheet.

3) Should I also sum “Vdd quiescent current” and "average current in VDD to the HB FET" ?

 

Andrew, be aware I edited the formula in #1. Q = I . dt, so I = Q/dt per cycle hence Iavg = Q/ts * fsw.

I did mean the orange ones, and it seems they give you an average figure of 100mA for the high side which sounds plausible for their max drive current and max gate capacitance at 500kHz/50%. It may be overkill for your arrangement, but that's not a bad thing. There's more discussion on this in the datasheet regarding sizing the bootstrap capacitor.

Use the operating currents; quiescent isn't relevant for power supply loading, more use for standby current when battery powered.

 

Andrew, be aware I edited the formula in #1. Q = I . dt, so I = Q/dt per cycle hence Iavg = Q/ts * fsw.

I did mean the orange ones, and it seems they give you an average figure of 100mA for the high side which sounds plausible for their max drive current and max gate capacitance at 500kHz/50%. It may be overkill for your arrangement, but that's not a bad thing. There's more discussion on this in the datasheet regarding sizing the bootstrap capacitor.

Use the operating currents; quiescent isn't relevant for power supply loading, more use for standby current when battery powered.

Hi,

1) So, if I wanted to calculate the total current of the gate driver, would I need to add VDD operating current to Iavg = Q/ts * fsw?
...I'm not entirely sure about this, because VDD operating current refers to the blue arrows, while Iavg refers to the orange ones
(see again image in #3) and I don’t know which of the two I should use (or whether to add them together)

2) I=dQ/dT --> Iavg = Qg*Fsw .. I don't understand your Iavg = Q/ts * fsw which results in Coulomb / s^2

 

Hi,

1) So, if I wanted to calculate the total current of the gate driver, would I need to add VDD operating current to Iavg = Q/ts * fsw?
...I'm not entirely sure about this, because VDD operating current refers to the blue arrows, while Iavg refers to the orange ones
(see again image in #3) and I don’t know which of the two I should use (or whether to add them together)

Yes, it is confusing. I need to read the datasheet in more detail. Normally the bootstrap boost for the high side MOSFET is external to the driver so the current for the high-side turn-on gate driver comes from the boost capacitor, which is then recharged from the supply via a blocking diode when the low-side MOSFET is on. In that case the current from supply to capacitor is determined by the differential voltage between the capacitor voltage after discharge to the supply voltage. Say you have a 100nF capacitor discharged to 10v from a 12v supply in 1uS (assuming fsw= 500kHz and 50% duty cycle), then you have a dV of 2v so dQ = 2 * 100e-9 = 200nC and i = dQ/dt = D . dQ/((1 - D)/fsw) which at D=50% simplifies to dQ . fsw = 200e-9 . 500e3 = 0.1A average.

The gate current for the lower MOSFET comes direct from VDD and that for the upper MOSFET from the boost capacitor which is charged from VDD during the lower MOSFET on time.

2) I=dQ/dT --> Iavg = Qg*Fsw .. I don't understand your Iavg = Q/ts * fsw which results in Coulomb / s^2

I did say it was from memory... peak gate current is Qc/ts. The maximum average input current over the complete cycle is, as you say Iavg = Qc . fsw, assuming D<=0.5.

Look at this example from another thread. The gate currents are 1.1A peak but for only 20nS twice per cycle, giving an average over the cycle of 8.3mA and the average current from the supply is only 8.7mA. The bulk of the heavy lifting is done by C3.

 

Yes, it is confusing. I need to read the datasheet in more detail. Normally the bootstrap boost for the high side MOSFET is external to the driver so the current for the high-side turn-on gate driver comes from the boost capacitor, which is then recharged from the supply via a blocking diode when the low-side MOSFET is on. In that case the current from supply to capacitor is determined by the differential voltage between the capacitor voltage after discharge to the supply voltage. Say you have a 100nF capacitor discharged to 10v from a 12v supply in 1uS (assuming fsw= 500kHz and 50% duty cycle), then you have a dV of 2v so dQ = 2 * 100e-9 = 200nC and i = dQ/dt = D . dQ/((1 - D)/fsw) which at D=50% simplifies to dQ . fsw = 200e-9 . 500e3 = 0.1A average.

The gate current for the lower MOSFET comes direct from VDD and that for the upper MOSFET from the boost capacitor which is charged from VDD during the lower MOSFET on time.


I did say it was from memory... peak gate current is Qc/ts. The maximum average input current over the complete cycle is, as you say Iavg = Qc . fsw, assuming D<=0.5.

Look at this example from another thread. The gate currents are 1.1A peak but for only 20nS twice per cycle, giving an average over the cycle of 8.3mA and the average current from the supply is only 8.7mA. The bulk of the heavy lifting is done by C3.

View attachment 365960

Hi,

on the one hand, I should simulate the circuit to find the waveforms as shown in the LTSpice screenshot you posted;
on the other hand, I’m fairly relaxed about it because I’ll be using a DC-DC converter that guarantees a maximum current of 2A… so, looking again at the block diagram in post #1, I’m sure we won’t even reach those levels

In any case, if I wanted to go into more detail, for my three-phase inverter I would use these MOSFETs, this gate driver and this DC-DC converter
Perhaps you’ll spot some ‘inconsistencies or incompatibilities’ between them that I’ve missed

 

I a

Hello everyone, I’m using Vishay’s Transim tool to design DC-DC converters, and during the initial configuration phase (where you set the minimum and maximum Vin, Iout, frequency, etc.), I’m asked to specify the output current that the DC-DC converter should deliver.

I have therefore drawn up a block diagram of the various integrated circuits that draw current on my future PCB.
The DC-DC converter in question is clearly the block on the left, and I want to know how much output current it will provide (i.e. the sum of the two blue arrows).

View attachment 365945


1) Correct me if I'm wrong, but I think the output current it will deliver is the sum of all the currents from the 'black' blocks (i.e. not the power NMOS), right?

2) If the answer is yes, in the various datasheets I look at:
2a: the maximum current at their Vdd (maximum current value)
2b: the quiescent current (minimum current value)

3) If I’ve got it right so far and I therefore calculate the maximum current as the sum of all the Imax values across the Vdd pins of the various blocks (the 2a solution) … should I enter a higher value in the simulator? (to allow for a sort of margin)

4) The LDO is linear, so its input current is equal to its output current (which is the sum of the currents from all the modules) + Iquiescent, isn't it?

I admire your thoroughness. I'd be inclined to take one look at it, decide "that'll not take more than an amp" and stick in an LMR38010. However, one day I might just be wrong - but there's always the 2A LMR38020 and I don't think I'll be THAT wrong.

One thing I did note was the 4th order filter on the output. I hope that terminal doesn't connect back to somewhere else in the circuit for voltage feedback? If so you have four poles in the transfer function, 360° phase shift and you've made an oscillator.

 

One thing I did note was the 4th order filter on the output. I hope that terminal doesn't connect back to somewhere else in the circuit for voltage feedback? If so you have four poles in the transfer function, 360° phase shift and you've made an oscillator

Hi, and thank you for your reply.

I’m not sure where the 4th-order filter is located.

 

I a

I admire your thoroughness. I'd be inclined to take one look at it, decide "that'll not take more than an amp" and stick in an LMR38010. However, one day I might just be wrong - but there's always the 2A LMR38020 and I don't think I'll be THAT wrong.

One thing I did note was the 4th order filter on the output. I hope that terminal doesn't connect back to somewhere else in the circuit for voltage feedback? If so you have four poles in the transfer function, 360° phase shift and you've made an oscillator.

I've tried to compare the LMR38020 with the Vishay SiC464 (which I’ve currently opted for), I haven't noticed any significant differences (correct me if I'm wrong) ... both certainly do their job well.

The LMR38020’s “Spread Spectrum” feature is interesting (though I haven’t looked into it in detail), and it could prove useful in my medical field (IEC60601)

 

Hi, and thank you for your reply.

I’m not sure where the 4th-order filter is located.

 

One thing I did note was the 4th order filter on the output. I hope that terminal doesn't connect back to somewhere else in the circuit for voltage feedback? If so you have four poles in the transfer function, 360° phase shift and you've made an oscillator

Ian, that was an example from another thread I was using to illustrate for Andrew the low average current needed for even moderately large gate currents. The output filter doesn't relate to his project.

 

on the one hand, I should simulate the circuit to find the waveforms as shown in the LTSpice screenshot you posted;
on the other hand, I’m fairly relaxed about it because I’ll be using a DC-DC converter that guarantees a maximum current of 2A… so, looking again at the block diagram in post #1, I’m sure we won’t even reach those levels

Ideally yes, though there are no Spice models from Renasas for those gate drivers. However its not hard to create a simulacrum for the gate driver element from the info in the data sheet. [edit] Renesas do have their own iSim: PE simulation for the ISL78424 but not, AFAIK, the ISL78434 though the difference is only the input side so for modelling gate drive performance that would work.

I think 2A will be more than adequate for the DC-DC converter. You don't need an LDO for 12v -> 3.3v, any fixed output linear regulator will suffice as you have plenty of headroom. However, if you are designing the DC-DC converter yourself, why not add a secondary 3.3v output rather than generate more heat from a linear regulator? Actually, I'd probably design it with the 3.3v as the primary regulated output and the 12v as the secondary as this is less critical on accuracy.

In any case, if I wanted to go into more detail, for my three-phase inverter I would use these MOSFETs, this gate driver and this DC-DC converter
Perhaps you’ll spot some ‘inconsistencies or incompatibilities’ between them that I’ve missed

No obvious issues, though not knowing what your inverter is driving I can't comment on suitability of the MOSFETs.

 

Ian, that was an example from another thread I was using to illustrate for Andrew the low average current needed for even moderately large gate currents. The output filter doesn't relate to his project.

Apologies. I thought it was his not yours.

 

Ideally yes, though there are no Spice models from Renasas for those gate drivers. However its not hard to create a simulacrum for the gate driver element from the info in the data sheet. [edit] Renesas do have their own iSim: PE simulation for the ISL78424 but not, AFAIK, the ISL78434 though the difference is only the input side so for modelling gate drive performance that would work.

I think 2A will be more than adequate for the DC-DC converter. You don't need an LDO for 12v -> 3.3v, any fixed output linear regulator will suffice as you have plenty of headroom. However, if you are designing the DC-DC converter yourself, why not add a secondary 3.3v output rather than generate more heat from a linear regulator? Actually, I'd probably design it with the 3.3v as the primary regulated output and the 12v as the secondary as this is less critical on accuracy.


No obvious issues, though not knowing what your inverter is driving I can't comment on suitability of the MOSFETs.

Hi, and thank you for your reply.

I’m trying to understand your sentence: "You don't need an LDO for 12v -> 3.3v, any fixed output linear regulator will suffice as you have plenty of headroom"
It's because there is a very large voltage drop? (from 12V to 3V) ..and that I would end up with very low efficiency (a lot of heat)
Or for other reasons?

SOLUTION 1:
I could use a linear regulator, but I’m worried that it too will get quite hot due to the output current draw (we’ve calculated around 200–300 mA, rounding up quite a bit).

SOLUTION 2
Should I therefore use an additional synchronous DC-DC buck converter after the first one? (like the TPS6214x or TPS62902)



@Ian0

 

I’m trying to understand your sentence: "You don't need an LDO for 12v -> 3.3v, any fixed output linear regulator will suffice as you have plenty of headroom"
It's because there is a very large voltage drop? (from 12V to 3V) ..and that I would end up with very low efficiency (a lot of heat)
Or for other reasons?

An LDO (low drop out) regulator is useful where you don't have any headroom - typically they will work with 150 - 300mV difference. Here you have plenty of headroom, so an LDO isn't required. However a standard regulator with a 12 - 3.3 = 8.7v drop will dissipate 0.87W per 100mA of current, so if your 3.3v demand is around the 100mA mark that's probably OK in an SMD part. Anything approaching 500mA, I'd go for a through-hole part. Alternatively, a switching regulator will lose maybe 10% of that, so one option, if your demand is that high is to use a 3-pin switching equivalent of the classic TO-220 cased regulator. Another option is to add an extra winding on the 48-12v buck converter's inductor to give around 5v out and use a standard 3.3v linear regulator off that, giving around 0.12W dissipation per 100mA, see below.

I could use a linear regulator, but I’m worried that it too will get quite hot due to the output current draw (we’ve calculated around 200–300 mA, rounding up quite a bit).
Should I therefore use an additional synchronous DC-DC buck converter after the first one? (like the TPS6214x or TPS62902)

Well, that would be an option, but you already have a buck converter, so why not extend that..., here's an example with the SiC431, but you can do it the same way with the SiC461. By keeping the voltage at the input of the 3.3v regulator to around 4v and using an LDO part as shown you could get 300mA with <300mW additional losses.