Hello allaboutcircuits!

The instructions for my task are above. There are no explicit restrictions, but I want to use flipflops for this one. We were taught no prior knowledge except basic gates and elementary logisim operation. I'm learning as I go and so far, an 11-state (0000-1010) up counter is what I've managed:



I'm lost where to go from here, especially about (1) how to make a down counter that starts from 10, and (2) how to implement both up and down counters with the direction input. I would appreciate any direction or reference.

Let me know what other information I could include in the thread.
Thank you very much.

 

You have a few issues.

As the clock ticks, which signal will change first? Is it really the one you have labeled LSB?

You are designing an asynchronous sequential logic circuit and there be demons in those waters. As your count advances, the outputs of the flip flops will not change instantly or simultaneously -- that's true even in the best-designed synchronous sequential circuits. You have a ripple counter, which guarantees that the outputs will change at different times, though pretty predictably. So in going from one state to the next, the counter will actually go through a sequence of states very quickly. If ANY of those happen to have the three bits that your AND gate is using HI at the same time, you will get a reset.

You should tie your set/reset inputs to an always-inactive state and use proper logic to effect the desired next-state transition -- unless you are willing to do the analysis needed to ensure that no critical races exist over the entire range of operating conditions.

Your first step is to prepare a state-transition diagram (or table), showing what state it show go to from each state of interest for each possible combination of control inputs.

 

As the clock ticks, which signal will change first? Is it really the one you have labeled LSB?

I realize the mistake about the LSB. I'm also reading up on mod-n counters from geeksforgeeks—From a section about ripple counters I understood better what you mean by outputs changing at different times.

If ANY of those happen to have the three bits that your AND gate is using HI at the same time, you will get a reset.

Thanks. I just understood what the AND gate is for in my up-counter attempt. Reset 1010 -> 0000 by ANDing the HIGH bits from 1010 and directing that to the resets. For the down counter, I'm thinking of a applying HIGH to presets and reset to do 1111 -> 1010.

Together in an up-down counter, I'm guessing it will look something like this:


Thanks again! Big help

 

Welcome to AAC!

There are no explicit restrictions, but I want to use flipflops for this one. We were taught no prior knowledge except basic gates and elementary logisim operation.

That's a big jump if you haven't been taught about flip flops and transition tables.

There isn't a generally accepted/taught formal method for designing asynchronous counters. It's usually done the way you've done it. Chain them together to make a binary counter and reset when the desired count is reached. The problem, as mentioned earlier, is that you have to contend with glitches when multiple outputs change at the same time.

If you're trying to use one counter for both digits, think about how you're going to decode the count of ten.

 

Here's design data for a binary up counter using RS flip flops:

The transition table is below the truth table. I don't show the corresponding columns in the truth table, but that's what is transferred to the Kmaps.

I always use A for the LSB.

 

I realize the mistake about the LSB. I'm also reading up on mod-n counters from geeksforgeeks—From a section about ripple counters I understood better what you mean by outputs changing at different times.



Thanks. I just understood what the AND gate is for in my up-counter attempt. Reset 1010 -> 0000 by ANDing the HIGH bits from 1010 and directing that to the resets. For the down counter, I'm thinking of a applying HIGH to presets and reset to do 1111 -> 1010.

Together in an up-down counter, I'm guessing it will look something like this:
View attachment 321872View attachment 321873

Thanks again! Big help

But you are ANDing together three bits, and 1010 only has two bits that are 1.

You aren't decoding 1010, you are decoding 1011. The idea is that it stays at 1010 for the full clock cycle, then as soon as it transitions to 1011, it immediately resets the counter to 0000. This happens so fast that anyone looking at the results will thing that it when from 1010 straight to 0000.

While a ripple counter that counts up is trivial (which is why they are so popular in electronics course), one that counts down is a bit more complicated. But once you have that, one that counts both ways is a straightforward enhancement. But in doing so, you have significantly complicated the amount of work to analyze the glitch states you have to deal with.

I'll say it again -- don't design asynchronous logic circuits unless you are prepared to do that analysis.

 

Together in an up-down counter, I'm guessing it will look something like this:

That's not a counter.

Are you certain you want to use an asynchronous counter? Up/down is no problem, but there could be issues with decoding counts. For example, when counting down from 8.

 

There is a fairly simple procedure for designing JK state machines documented here:
https://forum.allaboutcircuits.com/threads/making-a-counter-using-jk-flip-flops.129537/

Have not seen this in any textbook or technical article; but it is something I learned in graduate school at Case Western Reserve University about 50 years ago.