XOR gate in LT Spice

Thread Starter

MrsssSu

Joined Sep 28, 2021
201
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Hi people,
It has been quite a long time since I posted anything lately :)

Refering to the XOR gate schematic and truth table above from here, I have designed them in LT Spice. Higlighted in green are the 2 inputs and purple is output.However, to my surprise, when A and B are both true (A=5V , B=5V in LT Spice) , it does not really get pull down to 0. Is this normal and are these circuits normally contain an op amp to set the threshold voltage to make it either on or off (1 or 0 only) ? I have attached my LT Spice below for your convenience :).

Thank you and have a nice day:)
 

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crutschow

Joined Mar 14, 2008
30,116
it does not really get pull down to 0. Is this normal and are these circuits normally contain an op amp to set the threshold voltage
No.
Digital circuits contain only switching elements, not linear circuits like an op amp.

The base resistors are too small so you are getting an output voltage from the large base emitter current.
Change all the base input resistors to 10kΩ and rerun the simulation.

I trust your simulation is just for demonstration purposes as no real digital circuit is built with BJT transistors in the configuration you show.

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Thread Starter

MrsssSu

Joined Sep 28, 2021
201
No.
Digital circuits contain only switching elements, not linear circuits like an op amp.

The base resistors are too small so you are getting an output voltage from the large base emitter current.
Change all the base input resistors to 10kΩ and rerun the simulation.

I trust your simulation is just for demonstration purposes as no real digital circuit is built with BJT transistors in the configuration you show.

View attachment 269593
Thank you for your time :)
 

Alec_t

Joined Sep 17, 2013
12,897
when A and B are both true (A=5V , B=5V in LT Spice) , it does not really get pull down to 0.
Whether V1 and V4 are 10V or 5V, the simulation shows the output as only picoVolts at most. In the real world it would likely be greater because of transistor leakage currents. For TTL logic that generally wouldn't matter, since logic 0 is anything less than 0.8V.
 

Papabravo

Joined Feb 24, 2006
18,806
TTL is something you cannot simulate at this level because there is no such thing as a multi-emitter transistor. You could probably come up with a behavioral model, but I don't think you can "assemble" one with the available elements.

That said it is certainly possible to model DTL, RTL, and ECL gates if that is something that floats your boat.
 
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crutschow

Joined Mar 14, 2008
30,116
Here's a minimalist XOR gate that uses only two transistors and two resistors (three if you count the load resistor).

Note that the output voltage is essentially equal to the signal input voltage, reduced only by the small saturation voltage of the ON transistor.

It's powered from the input signals, but you could buffer the output with a powered emitter follower if you wanted a higher input and lower output impedance.

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