It has to do with open collector outputs. If you tie a bunch of collectors together sharing one resistor it is equivalent to an OR gate. It was a common practice in the days TTL logic was king.
To expand a bit on Bill's post, those open collector outputs are all pulled up with a single resistor. Thus any one output can pull the common line low.
It has an open collector output - the second paragraph of the intro on the data sheet stated that the device can be wire OR'ed. Open collector outputs are open collector outputs.
And of course wired OR can be accomplished by using series diode isolation between each of the 'voting' nodes and a single pull-up resistor so having open collector outputs is not the only way to be able to utilize wired OR stages.