The attached is MOS sampling circuit. In this circuit a MOS transistor can be use d as an analog switch, with its gate controlling the resistance between its source and drain.
In the triode region the transistor has Ron.
\(R_{on} = 1/(\c \mu _{n} c_{ox}\dfrac {W} {L}\left( V_{GS}-V_{TH}\right)\)
I want to know how can you know that the transistor will operate in triode region?
The only thing I know is that Vgs will be HIGH level but Vds is unknown.
Is there a way to make sure that Vds = Vin - Vout small when Vin changes with time?

 

In this case assuming that CK has two levels 5V and 0V.
At 0 V NMOS is off and at 5V NMOS is on. But according to NMOS Ids-Vds characteristic to make NMOS operating in triode region and acts as a resistor
Vds has to be very small. Then the characteristic can be considered linear and NMOS has a constant resistance Ron.
What I am confused here is that how can we make that condition(Vds is small)?
For example, when Vin = 1V and CK = 5V. At first the capacitor \(C_{H}\) isn't charged and therefore it has 0V across its plates. Now Vgs = 5V and Vds = 1V and assumes that the transistor will be in triode region and has Ron.
Now the circuit includes Vin, Ron and \(C_{H}\). The capacitor will be charged and its voltage will increase with time => Vds will decrease with time and therefore NMOS will continue in triode region and Ron = constant.
And I think this can be considered as a RC circuit with R = Ron = constant.

The NMOS will be in triode if Vgs - Vds < Vth or Vds > Vgs - Vth. Does this mean that the input voltage Vin has to be limited?
How about if the sampling signal Vin has amplitude larger?
I thought that amplitude has fixed amplitude but it seems wrong now.
I think with larger signal Vin in order to make NMOS operating in triode we have to change Vgs and therefore CK accordingly?
Is this right?

 

Could anyone confirm if I understand it right?

 

You are not trying to operate it in the triode region. You are trying to use it as a switch, which means you want it to go between having a channel resistance that is very, very high (ideally infinite) and a channel resistance that is very, very low (ideally zero).

One of the problems with the circuit you show is that you can't guarantee that the FET is turned on hard under all signal conditions. This is why most sampling circuits use two FETs, one NMOS and one PMOS, to make what is known as a transmission gate. The configuration you show should only be used if the circuit it is a part of constrains the signals to levels that will turn the FET on hard when it is "closed".

 

Thanks for reply!

You are not trying to operate it in the triode region. You are trying to use it as a switch, which means you want it to go between having a channel resistance that is very, very high (ideally infinite) and a channel resistance that is very, very low (ideally zero).

I understand it but my problem is that how can I make sure that the transistor will operate only in triode and cut-off regions.
With cut-off region, it is clear to me that when CK = 0V the transistor is cut-off.
(Assuming that Vin is larger than 0V)
But how about the triode, why it operate in triode in this case?
I have just redrawn the circuit above to analyse.

I know the condition for the transistor is in triode: Vgs > Vt and Vgs - Vt < Vds
but with this circuit I have no idea how to do it. I know the swing of Vgs under the swing of Vin but how can I compute Vds?
If I can draw the large signal characteristic Vin-Vout, I think I can choose Vin to assure that it operates in triode.

 

But WHY are you trying to ensure that it operates in the triode region?

Having said that, if it is being used as a switch and has low resistance, what do you know about the voltage across it when being used to sample a signal onto a capacitor once the switch has been closed for some amount of time?

 

But WHY are you trying to ensure that it operates in the triode region?

Because it plays the role of a switch. As you said, the switch only operates in two regions: cutoff and triode.
When CK = 0V => Vgs < 0 and the transistor is cutoff.
Now I want to make it operates in triode when CK = 5V.
If so:
Vgs = 5-Vin and Vds = Vout - Vin
And in order to operate in triode:
Vgs - Vt < Vds <=> 5 - Vin -Vt < Vout - Vin or Vout > 5 - Vt
I don't know what to do now

Having said that, if it is being used as a switch and has low resistance, what do you know about the voltage across it when being used to sample a signal onto a capacitor once the switch has been closed for some amount of time?

This is what I am confused. I only know it is equal to Vout - Vin but both Vin and Vout vary with time.

 

Where did I say that it can only operate in either cutoff or triode?

And where are you getting that, in order to be in the triode region, you need Vds to be greater than (Vgs-Vth)? You might want to look that up again.

If you are "sampling" a signal, don't you want the sample to equal the signal? What does that say about the Vds at the end of the sampling event?

 

Where did I say that it can only operate in either cutoff or triode?

You are not trying to operate it in the triode region. You are trying to use it as a switch, which means you want it to go between having a channel resistance that is very, very high (ideally infinite) and a channel resistance that is very, very low (ideally zero).
From this, I think you meant it has to operate only in triode and cutoff.
What is wrong with this?

And where are you getting that, in order to be in the triode region, you need Vds to be greater than (Vgs-Vth)? You might want to look that up again.

Oh, sorry I was mistaken. I meant Vds< Vgs - Vth and Vgs> Vth.

If you are "sampling" a signal, don't you want the sample to equal the signal? What does that say about the Vds at the end of the sampling event?

Yes, I thought about this. We want the sample as close to the sampling signal as possible.
But before this, I have to make sure that the transistor is in triode and cutoff.
Then I think "sampled signal is equal to sampling signal" is the result of transistor operating in triode region. Therefore, I didn't use this.
Is this is what I am wrong?
I even can't imagine how the circuit can start to operate.
For example, initially, at the time t=0, the voltage across the capacitor is 0V
and Vin = 2V.
I can compute as follows:
Vgs = 5 - Vin= 5 - 2 = 3V. Assume that Vth =0.7V then Vgs - Vth = 2.3V
Vds = -2V???
MOSFET is symmetry device then in this case D and S are exchanged its role?
And I recompute these voltages:
Vgs = Vg - Vs = 5 -0 =5V (in this case S is the pole connected with capacitor)
Vds = Vd - Vs = Vin -0 = 2V.
And then Vgs - Vth = 5 - 0.7 = 4.3 V and Vds= 2 V.
Vgs -Vth > Vds and the transistor operates in triode and the capacitor is charged through Ron to the voltage Vin= 2V.
After this, CK = 0V the capacitor discharge through Rload and eventually its voltage go back to 0V.
Aha, I think I work out this, right?
After the time, the process is repeated as above.
And if, for example, MOSFET isn't a symmetry device then we can't sample an AC signal, right?

 

So, I say that you are NOT trying to operate in the triode mode and you conclude from that that I am saying it HAS to operate in the triode mode? The logic escapes me.

You just want the damn thing to be ON! The harder, the better. You want Vgs to be as large as you can get it. If you can get it into saturation, great! For a given Vds, that will give you the lowest channel resistance you can get, which is what you want. As the voltages equalize, it will drop into the triode region naturally not because that's what you want, but because that's just what happens as Vds falls toward zero.

 

You just want the damn thing to be ON! The harder, the better. You want Vgs to be as large as you can get it. If you can get it into saturation, great!

Sorry, I don't get what you mean here!

For a given Vds, that will give you the lowest channel resistance you can get, which is what you want. As the voltages equalize, it will drop into the triode region naturally not because that's what you want, but because that's just what happens as Vds falls toward zero.

I'd like to know if small Vds causes small Ron or vice versus.
And to be sure, I think the sampling circuit above isn't complete, right?
Does it need a resistor RL to discharge the voltage in the capacitor each time CK go low?
And each time sampling the capacitor voltage is 0V?

 

I'd like to know if small Vds causes small Ron or vice versus.

That's actually a nonsensical question. It's like asking if the voltage across a resistor causes the current or the current through a resistor causes the voltage. Because we like to think in terms of voltage being the driver of things, we naturally think in terms of voltage causing a current, but the reality is that they are merely two parameters that are related to each other by the resistance and therefore you can think of it either way.

In the case of Ron, I would say that it is reasonable to consider Ron a consequence of Vgs and Vds with Ids resulting from that, but it is really a parameter that describes a relationship between Vds and Vgs so you could choose to think of it as a consequence of Vgs and Ids with Vds resulting from that.

And to be sure, I think the sampling circuit above isn't complete, right?
Does it need a resistor RL to discharge the voltage in the capacitor each time CK go low?
And each time sampling the capacitor voltage is 0V?

Each time you turn on the switch, the voltage on the capacitor will go to the signal voltage is given enough time to settle. You don't need to discharge it at all. If the last sample was of a higher voltage, then current will flow off the capacitor. If the last sampel was of a lower voltage, then current will flow onto the capacitor.

In practice, where feasible, you like to reset the sampling capacitor's voltage between samples because otherwise the final voltage that it settles at when you turn off the switch will be influenced by the prior sample value and thus become a source of crosstralk between samples. But this is a noise abatement issue and not a fundamental circuit functionality issue.

 

Thanks! That is what I am looking for.
Now the problem is that how can I make sure that the transistor is in triode when CK is HIGH(5V in this example).
Please see the picture bellow.

For example, the last sample is -1V, and this means that the voltage across the capacitor is -1V.
Now the next Vin is 7V then I have:
Vgs= Vg - Vs = 5 - (-1) = 6V
Vds = 7 - (-1) = 8V
From this we have Vgs - Vth = 6-0.7 = 5.3V < Vds = 8V
=> The transistor isn't in triode region
How can I resolve the situation?
I don't know how to determine the swing of Vin to make sure that the transistor always operate in triode when CK is HIGH (5V).
It is hard for me because the voltage across the capacitor varies with time and therefore Vds also changes with time???

 

Thanks! That is what I am looking for.
Now the problem is that how can I make sure that the transistor is in triode when CK is HIGH(5V in this example).

Again, WHY DO YOU @#*$%^& CARE if it is in the triode region or in the constant current region?!?!?!?!?!?!?!?!

You are using it AS A SWITCH!!!!!!

Please see the picture bellow.

For example, the last sample is -1V, and this means that the voltage across the capacitor is -1V.
Now the next Vin is 7V then I have:
Vgs= Vg - Vs = 5 - (-1) = 6V
Vds = 7 - (-1) = 8V
From this we have Vgs - Vth = 6-0.7 = 5.3V < Vds = 8V
=> The transistor isn't in triode region

SO @#*$%^& WHAT?!?!?!

Is it ON?

Is the capacitor voltage moving toward becoming equal to the signal voltage?

Would being in the triode region make it move faster?

How can I resolve the situation?
I don't know how to determine the swing of Vin to make sure that the transistor always operate in triode when CK is HIGH (5V).
It is hard for me because the voltage across the capacitor varies with time and therefore Vds also changes with time???

You KEEP on insisting on trying to keep the transistor in the triode region when it is ON yet, despire repeated attempts to get you to, you won't give ONE reason why you WANT it to always be in the triode region when it is ON. What horrible thing will happen if it is in the active region when first turned on?

 

I am totally confused!

You are using it AS A SWITCH

Yes, as for me in order to make it as a SWITCH, I have to make it operate in triode and cut-off region.
When it is in cut-off: Rds is very large and the it is almost open between D and S.
When it is in triode: Rds is small. Ideally, it is 0Ω.

Again, WHY DO YOU @#*$%^& CARE if it is in the triode region or in the constant current region?!?!?!?!?!?!?!?!

Because if the transistor is in saturation region Rds is very large, maybe ∞ and then the capacitor isn't charged at all.
IF it is in triode then Rds is small and the capacitor is charged through this resistor and the sampling process is done.

Is the capacitor voltage moving toward becoming equal to the signal voltage?

Would being in the triode region make it move faster?

Yes, for me, if transistor is in saturation region, Rds is ∞ and the capacitor voltage can't move toward becoming equal to the signal voltage. The voltage in capacitor remain unchanged and we can't sample signal.
If transistor is in triode, Rds is small and the capacitor will quickly charge to the signal voltage.

 

Where are you getting that if the FET is in the active (i.e., saturation) region that the Rds is infinite? If it is infinite, then no current can flow. We already have a name for that regions -- it's called cutoff!

Sure, it would be NICE to increase Vgs to put it into the tride region, but it is most certainly turned on in the active region as well. Unless you want to constrain your input voltage to very small levels, you have to accept that for some signals it will start out in the active region and, as the voltage equalizes, that it will move into the triode region.

If you REALLY insist on making sure that it is ALWAYS in the triode region, then require that the input voltage never change by enough to put it out of the triode region regardless of what the prior sampled signal was either by requiring that the amplitude of the input signal be small enough or that the voltage applied to the gate is large enough.

 

Where are you getting that if the FET is in the active (i.e., saturation) region that the Rds is infinite?

It is what I think because when in saturation it acts as a current source. And therefore Rds is infinite.

If it is infinite, then no current can flow.

How about the case current source?

Sure, it would be NICE to increase Vgs to put it into the tride region, but it is most certainly turned on in the active region as well. Unless you want to constrain your input voltage to very small levels, you have to accept that for some signals it will start out in the active region and, as the voltage equalizes, that it will move into the triode region.

Well, I din't know that SWITCH can operate in active region. If so in this case I think you have consider both r0 between D and S when it is in saturation.
If so then Req (the equivalent resistance of current and r0) will be r0.
And it seems appropriate to use active region.
But in the situation I don't consider r0, then Req = R(current source) =∞ and I can use active region.
Hm... Two ways give quite different results!

If you REALLY insist on making sure that it is ALWAYS in the triode region, then require that the input voltage never change by enough to put it out of the triode region regardless of what the prior sampled signal was either by requiring that the amplitude of the input signal be small enough or that the voltage applied to the gate is large enough.

This is also what I was confused. In this case, how can I compute input swing?
I din't know that saturation can be used.
If I can use saturation, then I am happy and don't care about the input swing.

 

It is what I think because when in saturation it acts as a current source. And therefore Rds is infinite.

AHHHH. Now we are truly getting somewhere!

And this is why I am always asking people to explain their REASONING for things.

The nominally infinite OUTPUT resistance of a current source is completely different that the effective channel resistance.

The output impedance of a current source is defined as

Rout = dV/dI

or, equivalently

1/Rout = dI/dV

Which is the amount by which the output current CHANGES as a result of a CHANGE in the output voltage. If the output current does not change if you change the output voltage, then 1/Rout is zero meaning that Rout is infinite.

But the effective channel resistance is

Ron = Vds/Ids

The key thing to note is that the output resistance is a CHANGE in output current, while the channel resistance is the TOTAL output current.

Two very different things.

This is also what I was confused. In this case, how can I compute input swing?
I din't know that saturation can be used.
If I can use saturation, then I am happy and don't care about the input swing.

If you can keep the transistor not only in the triode region but also in the early part of the triode region where the characteristic curve is nearly linear, then it allows you to treat the transistor as a fixed resistor when it is ON and that allows you to calculate a time constant which permits you to ensure that your sampled voltage reaches some fairly constant fraction of the signal voltage (provided you reset it each time). In this case you are NOT using it just as a switch, but instead as a filter element. But this requires either very large Vgs values or very small Vin swings (and it is a pretty simple matter to compute the bounds). If you want large Vin swings relative to your Vgs drive capabilities, then you need to run the worst case numbers (or a sim) to see how long your ON time has to be in order to get the capacitor voltage to settle within an acceptably small difference from the signal value.

 

Thanks! Finally, I got it.
The last post is all what I was confused. Not knowing the difference beween infinite OUTPUT resistance of a current source and the effective channel resistance also made me confused.

 

Yep!

It's a pretty subtle concept that is usually not made very clear and it really easy to not pick up on on your own until you have a much stronger fundamental and/or intuitive feel for small signal analysis.