I have this 74LS375 latch in this circuit, but the way it's wired up, it makes no sense to me.
Attached is the IC as it's currently wired up, the equivalent circuit from the datasheet, and the logic equivalent of permanently tying the latch enable line to 5V.
I don't get it. It's just the clock signal to the 8279 display / keyboard driver. The ClkE signal is just the master clock after it's passed through the buffer from the logic board, and the Clk signal proceeds directly from there into the 8279.
If I just needed a bit more propagation delay for whatever reason, I have half of a 74LS241 buffer IC sitting idle... couldn't I just feed this signal through there?
Attached is the IC as it's currently wired up, the equivalent circuit from the datasheet, and the logic equivalent of permanently tying the latch enable line to 5V.
I don't get it. It's just the clock signal to the 8279 display / keyboard driver. The ClkE signal is just the master clock after it's passed through the buffer from the logic board, and the Clk signal proceeds directly from there into the 8279.
If I just needed a bit more propagation delay for whatever reason, I have half of a 74LS241 buffer IC sitting idle... couldn't I just feed this signal through there?
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