I have this XOR frequency doubler build with TTL

And I cannot understand why capacitor voltage do not reach 0V.
Any ideas why ?

 

Forget all this, I see it is a HC part.

 

What is the value of R1?

 

Forget all this, I see it is a HC part.

Why ??

What is the value of R1?

I don't know, but I will try to find out. Are you suspect voltage divider (R1 and scope probe)?

 

What is the driving source? It looks like little to no charge is coming off the HC input with the driving source at GND. If you make the frequency of the input very low does it drop further?

 

what is the REAL part number that you use.... (74??86)?

74HC is CMOS logic with TTL pinout. if you are using real TTL chip then of course voltage will not drop below 1.6V or so... to understand why, you need to look into internal circuit of the gate.

you can get rid of RC and just use another gate in place of R (to generate propagation delay).

 

what is the REAL part number that you use.... (74??86)?

74HC is CMOS logic with TTL pinout. if you are using real TTL chip then of course voltage will not drop below 1.6V or so... to understand why, you need to look into internal circuit of the gate.

you can get rid of RC and just use another gate in place of R (to generate propagation delay).

The HC parts have TTL pinouts with CMOS thresholds (Vcc/2). The HCT parts have TTL pinouts and TTL thresholds (0.8V & 2.0V). A regular TTL input will source 1.6 mA from an input which might explain the observed behavior. An LS gate will source one fourth of that for an apparent voltage of 0.4 VDC.

 

what is the REAL part number that you use.... (74??86)?

74HC is CMOS logic with TTL pinout. if you are using real TTL chip then of course voltage will not drop below 1.6V or so... to understand why, you need to look into internal circuit of the gate.

you can get rid of RC and just use another gate in place of R (to generate propagation delay).

Bingo, Low level input current from 74S86 and big R1 (33kΩ) resistor value caused the problem. Thanks for reminding me about this, what a stupid mistake.

 

Bingo, Low level input current from 74S86 and big R1 (33kΩ) resistor value caused the problem.

Still not clear to me. What was driving pin 1? That's what should be discharging the cap. What is the frequency? What is the cap value?

What is the part number of the XNOR? You mentioned HC and S.

 

What was driving pin 1? That's what should be discharging the cap.

Signal gen and without the gate the signal look like this

What is the frequency?

50kHz

What is the cap value?

22pF

What is the part number of the XNOR? You mentioned HC and S.

74S86

 

Signal gen and without the gate the signal look like this

Would think that the signal generator would be able to sink enough current to discharge the cap. Is the red waveform with the integrator?

 

Yes, the red waveform from post #10 shows the voltage across the cap without the gate in the circuit.

 

Yes, the red waveform from post #10 shows the voltage across the cap without the gate in the circuit.

Still doesn't make sense. The input of 74S86 (which is an XOR, not an XNOR as shown in post #1), is the emitter of an NPN transistor. The signal generator would need to sink at most another 1.6mA.

 

Still doesn't make sense.

Why?

 

Why?

Because the signal generator or any other 74S gate should have no problem driving 2 74S inputs with an additional 22pF of capacitance.

The correct max input current is -2mA; the -1.6mA was for 7486.

 

But as you can see at the red waveform from post #10t the signal generator is able to sink all this current and discharge the cap to almost 0V, isn't it?

 

But as you can see at the red waveform from post #10t the signal generator is able to sink all this current and discharge the cap to almost 0V, isn't it?

Yes. My question is why it can't do it with the XOR gate. Max input current for 2 74S inputs would be -4mA; the signal generator should be able to handle that.

As an experiment, you could try driving both inputs of the XOR without the integrator.

 

The RC network's purpose is to create a delay, so that either edge on the input produces a pulse on the output.
Something else doesn't make sense. The TC for 33 KΩ and 22 pf is approximately .75 μsec and yet we see rise and fall times at the capacitor which appear to be at least an order of magnitude larger.

 

The RC network's purpose is to create a delay, so that either edge on the input produces a pulse on the output.

If you're responding to my "doesn't make sense" posts, I'm trying to understand why the signal generator can't sink 4mA and discharge the cap.

 

If you're responding to my "doesn't make sense" posts, I'm trying to understand why the signal generator can't sink 4mA and discharge the cap.

No, I'm trying to say the the RC is not an integrator. I agree, that something does not make sense, I just cant put my finger on it. I do agree that the signal generator should be able to sink some amount of current, but I've never actually looked at the specs of one to know how much that should be. I also don't know if this is an analog output adjusted to look like a logic output, or an actual logic output like a 48 mA bus driver or something.