Hi,
Problem statement: I am using SPI communication from microcontroller to slave with quad channel buffer in between so the signal path is


CONTROLLER<->BUFFER<->SLAVE

MISO, MOSI, CLK, CS are passing to slave via buffer from controller.
I am operating SPI at 8MHZ,2.4V, SPI mode 0. the buffer has a delay of 30ns.
How can I know what is the maximum delay that can be afforded by the controller?
Is there any way/ tool I can simulate this setup?

 

What do you mean by "the buffer has a delay of 30ns" ?

If the SPI is clocked at 8MHz, the clock period is 125ns.
Let's assume that you have a 50ns window to latch the data.

If both CLOCK and DATA are delayed by 30ns, then there should not be a problem.
If only one is delayed by 30ns, then you should still be ok.

 

The max delay also depends on the SPI circuit design and SPI hardware.

You can use a SPI Master With Signal Path Delay Compensation or you can use something like the clock loopback method if you have a spare SPI port for the loopback data.

Isolated SPI Bus With Clock Loopback
To communicate with SPI peripherals at high speed and/or across long distances, it is necessary to compensate for the propagation delay of the data link. The most commonly applied method is to loop back the master clock via a separate data line, which resembles the receive clock to provide synchronicity for the receive data sent by the slave (Fig. 5).

In transmit direction, the data sent by the master stay in synch with the master clock and can be easily read by the slave. In the opposite or receive direction, data sent by the slave traverse synchronously with the looped-back clock as both experience the same prop-delay through the isolator (Fig. 6).

Because both data streams, in transmit and receive, now possess their own clock to which they run synchronously, the data link is independent of propagation delay and clock speed and allows for maximum speed utilization.

https://www.electronicdesign.com/te...speed-spi-bus-despite-long-propagation-delays

 

What do you mean by "the buffer has a delay of 30ns" ?

If the SPI is clocked at 8MHz, the clock period is 125ns.
Let's assume that you have a 50ns window to latch the data.

If both CLOCK and DATA are delayed by 30ns, then there should not be a problem.
If only one is delayed by 30ns, then you should still be ok.

propagation delay in buffer is 30ns.

 

propagation delay in buffer is 30ns.

We need a schematic showing how may buffers and on what lines.
I think you have buffers on all lines. MISO, MOSI, CLK, CS
If CLK and MOSI have buffers the two signals will arrive at the same time to the slave.
If CLK and MISO have buffers the CLK is delayed 30nS and the data coming back is also delayed 30nS giving a delay of 60nS. The master will see a delayed data.

 

propagation delay in buffer is 30ns.

the buffer has a delay of 30ns = propagation delay in buffer is 30ns
Sweet. Good to know.
Why is this a problem?

 

FYI. SPI does not have a requirement for the clock to be a fixed frequency or even that all bits be the same length. You could quite literally stop all signal changes in the middle of a bit and pick up where you left off a day later. Normally it would require a processor bit-banging the interface to perform this experiment

 

We need a schematic showing how may buffers and on what lines.
I think you have buffers on all lines. MISO, MOSI, CLK, CS
If CLK and MOSI have buffers the two signals will arrive at the same time to the slave.
If CLK and MISO have buffers the CLK is delayed 30nS and the data coming back is also delayed 30nS giving a delay of 60nS. The master will see a delayed data.

Yes all the MISO, MOSI, CLK, CS has buffers.

 

the buffer has a delay of 30ns = propagation delay in buffer is 30ns
Sweet. Good to know.
Why is this a problem?

here is the datasheet of buffer.
https://www.mouser.in/ProductDetail/Texas-Instruments/SN74HCS126QPWRQ1?qs=W/MpXkg%2BdQ5drcxwkY6Oww==

 

here is the datasheet of buffer.
https://www.mouser.in/ProductDetail/Texas-Instruments/SN74HCS126QPWRQ1?qs=W/MpXkg%2BdQ5drcxwkY6Oww==

I would like to understand what the maximum SPI clock freqency i can run? how to calculate theoretically

 

I would like to understand what the maximum SPI clock freqency i can run? how to calculate theoretically

It depends on what frequency the peripherals can handle. You have to read each and every peripheral datasheet. These will be practical limits rather than theoretical limits. If a theoretical limit exists it will be related to the transmission line distance between the chips. If two die are placed on the same substrate the theoretical and practical limit will increase to higher frequencies.