Calculating maximum delay

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Dija Angel

Joined Oct 1, 2021
33
Hello everyone! From what I'm taught when the flip flop goes to the xor gate it leads to two possible outcomes(the output could either go high or low) and I'm confused as to why this is true?

Also is this the same as for an XNOR gate.
 

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dl324

Joined Mar 30, 2015
16,917
From what I'm taught when the flip flop goes to the xor gate it leads to two possible outcomes(the output could either go high or low) and I'm confused as to why this is true?
That's the nature of all 2 input gates (excluding tri-state). Sometimes the output is HIGH, sometimes it's LOW.
Also is this the same as for an XNOR gate.
XNOR is XOR inverted.

gates.jpg
It's a solution to an exam paper
What the numbers mean is unclear and most of the gates that should have at least 2 inputs only have one drawn.
 

Thread Starter

Dija Angel

Joined Oct 1, 2021
33
Thanks for your response! Here's the question for more clarification,it seems that when doing these kind of questions only one input is accounted for and thats what leads to my confusion :)
 

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WBahn

Joined Mar 31, 2012
30,055
Thanks for your response! Here's the question for more clarification,it seems that when doing these kind of questions only one input is accounted for and thats what leads to my confusion :)
It would be nice to have Figure 4.

The question is asking about the critical delay path. That will be a single path from one end of the signal chain to the other, so it will usually go through, at most, one input of a given gate. If Input A on a particular gate is on the critical path, that means that Input B is not, which is because the relative timing of the signals at A and B, combined with the logic function in question, is such that signal at Input A will exert influence after the signal at Input B has already had time to have its say.
 

Thread Starter

Dija Angel

Joined Oct 1, 2021
33
Thank you for your response! I didn't show figure 4 because I'm familiar with solving the question and the critical path my only issue was this solution where an xor gate leads to two possible outcomes(the output could either go high or low) and I'm confused as to why this is true because it only has one input? :)
 

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WBahn

Joined Mar 31, 2012
30,055
Thank you for your response! I didn't show figure 4 because I'm familiar with solving the question and the critical path my only issue was this solution where an xor gate leads to two possible outcomes(the output could either go high or low) and I'm confused as to why this is true because it only has one input? :)
No, it has two inputs. While only one of them might be on the critical path, the output is still a function of both. Just consider the case where the other input is stable at a LO value when the FF output changes verses if the other input is stable at a HI value. You also have to allow for the two different situations created by the FF output going HI-to-LO and going LO-to-HI. There is nothing that guarantees that the critical path is the same for both situations. You have to look for the worst of the worst -- that is your true critical path. You can put bounds of that path by making some assumptions, such as the delay for any given element being the slowest of the delays for that type of gate, or even using the slowest delay of any gate as being the delay for every gate. That allows you to get an answer quickly and if that answer is good enough, then you are done because the actual situation will be better.

Of course, on an exam problem, that is seldom the route to go.
 

WBahn

Joined Mar 31, 2012
30,055
Ah ok thank you so much! And would this be the same when considering an XNOR gate?
It's the same with any gate, but it more relevant with XOR/XNOR gates because one input inverts the behavior of the other. For most gates, each input can effectively either enable to disable the other input, so for critical path considerations you have to assume that the other input is enabling the critical-path signal.
 
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