What can be done to pull down the output to zero?

Thread Starter

Siddharth Singh 3

Joined Jun 17, 2019
24
I have designed a CMOS inverter where VDD=10V and Vg is pulsating input with maximum amplitude=1.8V. However, when I plotted its waveform, the output was not pulled down to zero.
Why is this happening? Is there anything that can be done in order to pull down the output to zero?
 

StefanZe

Joined Nov 6, 2019
191
Your high side mosfet ist probably not turning off because the Vsg will not go down low enough.
Please post a schematic of your circuit.
 

BobTPH

Joined Jun 5, 2013
9,149
If Vdd is 10V, why would you think 1.8V would set the output low? I would expect at least 5V to be the minimum for a high input.
 

crutschow

Joined Mar 14, 2008
34,686
Normally the signal input to a CMOS inverter is equal to the supply voltage, so that one device is fully on, and the other is fully off.
 

StefanZe

Joined Nov 6, 2019
191
Your p-Mosfet is in shown the wrong way. Your source and drain are wrong (switch them). But this does not change your problem that the p-Mosfet will not switch of with a voltage of only 1.8V. I'm not even sure your n-Mosfet will turn on with this gate voltage.

Try a resistor instead of the p-mosfet. This will give you an inverter if the n-Mosfet is able to switch on and off with 1.8V. The output current will be limited because of the resistor. If you need more current you can use 2 normal CMOS inverter after this stage.
 

crutschow

Joined Mar 14, 2008
34,686
Can we add another circuit that will pull down the output?
Don't see how at the output.

You need a transistor-resistor level shifter circuit at the input to generate a 10V signal to drive your inverter.
That needs to be either an N-MOSFET that can switch with a 1.8V input, or an NPN bipolar transistor (BJT).
 
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