Hi all,

I am new to VHDL. Can someone please explain what is the difference between std_logic and std_logic_vactor ?

 

std_logic describes a single, 9-valued signal taking any value of: '0', '1', 'Z', 'X', 'W', 'H', 'L', '-', and 'Z'.

The std_logic_vector is a bus, or group of std_logic signals.

 

When using std_logic_vector, one specifies the number of signals grouped into a bus using indicies in the signal declaration, ie;_

std_logic_vector [31 downto 0] my_signal;