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VHDL modelling and logic synthesis

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samieee

Joined Apr 15, 2010
1
hi all

I am studying in electrical engineering in 9th semester.In our university we have an elective course named vhdl modelling and login sysnthesis.I want to know how much important is this course?In which fields it is used? Should I take it?
thanks in advance
.....
 
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