VHDL - delay before switching...

Thread Starter

pmd34

Joined Feb 22, 2014
507
I'm a bit new to VHDL, i am using quartus prime, and ultimately a MAXII CPLD device.
I want to make some VHDL code for a half bridge fet driver, so I want to switch one output off.. wait some ns.. then switch the other output on.. I would prefer to do this without using a global clock signal if possible.

I'm a bit unclear how to do this in VHDL can I use WAIT, TRANSPORT or... ?
It is also unclear to me if these are "real" delays that will be inserted into the timing when I program the chip, or if they are just simulation timings, or visa versa.
 

kubeek

Joined Sep 20, 2005
5,724
as far as i remeber delays like that cannot be synthesized into real hardware. How long is the time you want to wait?
s
 

Thread Starter

pmd34

Joined Feb 22, 2014
507
A few micro seconds I guess.. basically I want to be able to program in a time delay between switching one fet off and the other on to prevent cross over, but I may end up with a variable clock frequency else where on the chip...
I was thinking I might simply have to add in a use of a timmer with say the on chip oscillator.
 

kubeek

Joined Sep 20, 2005
5,724
I would just go and implement a counter circuit that will wait for some number of clock cycles and then set the output.
 

Thread Starter

pmd34

Joined Feb 22, 2014
507
I would just go and implement a counter circuit that will wait for some number of clock cycles and then set the output.
Yup I guess its the way! Many thanks!

Actually I wonder if I might pick your brains whilst on the subject.. I want to do some high speed PWM with the CPLD.. I see most don't actually have very fast oscillators built in. Is there a reason for this? And any reason why it would be bad to have high speed clock module externally to supply the signal.. eg. a 100MHz oscillator module?
 

kubeek

Joined Sep 20, 2005
5,724
Ok many thanks for the help!
No problem, feel free to ask. My vhdl is very rusty and verilog just a bit less, but I think the major ideas of how it works are still there.
Does your IDE have a simulator that can verify the timing after the gates are placed on the cpld?
 

Thread Starter

pmd34

Joined Feb 22, 2014
507
No problem, feel free to ask. My vhdl is very rusty and verilog just a bit less, but I think the major ideas of how it works are still there.
Does your IDE have a simulator that can verify the timing after the gates are placed on the cpld?
Much appreciated! To answer your question... probably! :pIm using Altera Quartus Lite, and sort of only just getting to grips with it. I have managed to figure out how to run the VDHL simulation part but I guess I am not SO confident that I know where simulation and reality will differ!
 
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