I'm a bit new to VHDL, i am using quartus prime, and ultimately a MAXII CPLD device.
I want to make some VHDL code for a half bridge fet driver, so I want to switch one output off.. wait some ns.. then switch the other output on.. I would prefer to do this without using a global clock signal if possible.
I'm a bit unclear how to do this in VHDL can I use WAIT, TRANSPORT or... ?
It is also unclear to me if these are "real" delays that will be inserted into the timing when I program the chip, or if they are just simulation timings, or visa versa.
I want to make some VHDL code for a half bridge fet driver, so I want to switch one output off.. wait some ns.. then switch the other output on.. I would prefer to do this without using a global clock signal if possible.
I'm a bit unclear how to do this in VHDL can I use WAIT, TRANSPORT or... ?
It is also unclear to me if these are "real" delays that will be inserted into the timing when I program the chip, or if they are just simulation timings, or visa versa.