How would I modify the following code so that clear is asynchronous?

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;

Untity Four_Bit_Register is
    Port (
        Clear        : in  std_logic;
        Inc           : in  std_logic; -- x
            Clock       : in  std_logic;
    Cnt_in        : in std_logic_vector(3 downto 0);       
            Cnt_out    : out std_logic_vector(3 downto 0);
    Load            : in std_logic);    
End Four_Bit_Register;

Architecture Four_Bit_Register_Arch of Four_Bit_Register is
 
Signal Cnt    : std_logic_vector (3 downto 0);    

Begin
 Cnt_out <= Cnt;
  
  Count : Process( Clear, Inc, Clock, Load)
  
Begin
   
    if clock'event and Clock = '1' then
    
    if Clear = '1' then
             Cnt    <= "0000";
elsif Load = '1' then 
        Cnt <= Cnt_in;
elsif Inc = '1' then
              Cnt    <= Cnt + "0001";
         else
             Cnt    <= Cnt;
            End if;    
End if;
End process;

end Four_Bit_Register_Arch;

Would I just change Cnt<="0000";
To Cnt<="1111";

 

Take the clear function out of the process branch or put it before the clock .