I tried to solve this code but ı couldn't deal with it drawing the logic circuit and create a truth table for a 3-to-8 decoder with enable on vhdl.in the normal situation,it runs but ı could not add std_logic_vector and enable,how can ı do this ?

 

You might look up the data on 74HC138, shows schematic & truth table.

 

You should start by posting what you have and what you mean by

ı could not add std_logic_vector and enable

.

Simply saying you have a problem in some far off code does not allow us to help you.

 

1. I want to draw the logic circuit and create a truth table for a 3-to-8 decoder with ENABLE on Vhdl.
2. Using ONLY concurrent statements (signal assignments), write a VHDL code for a 3-to-8 decoder with ENABLE. I need to use only of std_logic_vector type for input and output.
3. There are usually 8 tests to perform with enable set to ‘1’. Iwant to add 2 more tests with enable set to ‘0’
4. Using Selected Signal Assignments (SSA), I want to write another VHDL code for a 3-to-8 decoder without ENABLE.
5. Create an UCF file for testing.
6. it is what I mean:

 

1. I want to draw the logic circuit and create a truth table for a 3-to-8 decoder with ENABLE on Vhdl.
2. Using ONLY concurrent statements (signal assignments), write a VHDL code for a 3-to-8 decoder with ENABLE. I need to use only of std_logic_vector type for input and output.
3. There are usually 8 tests to perform with enable set to ‘1’. Iwant to add 2 more tests with enable set to ‘0’
4. Using Selected Signal Assignments (SSA), I want to write another VHDL code for a 3-to-8 decoder without ENABLE.
5. Create an UCF file for testing.
6. it is what I mean:

First, VHDL is a description language and is not drawn.

Again, you are not posting your code. It is impossible to tell you what you are doing wrong when you aren't showing us what you're doing in the first place.

Do you know how to make a 3-to-8 decoder? Do you know VHDL? What is the problem you are having?