Using Latches For Bus Expansion ?

Thread Starter

HalfMadDad

Joined Jun 10, 2016
43
Hi Everyone.
I mostly service circuit boards and there are gaps in my knowledge with design.
With most boards I work on, the designers used FPGA chips to increase the number of chips that can be controlled through tri-state logic. Sometimes I wonder if this was simply done to use FPGAs as they are hard to copy.
Would there be any harm in using latches to increase the number of control bus lines?
Thanks for reading-Patrick
 

Papabravo

Joined Feb 24, 2006
18,068
Hi Everyone.
I mostly service circuit boards and there are gaps in my knowledge with design.
With most boards I work on, the designers used FPGA chips to increase the number of chips that can be controlled through tri-state logic. Sometimes I wonder if this was simply done to use FPGAs as they are hard to copy.
Would there be any harm in using latches to increase the number of control bus lines?
Thanks for reading-Patrick
I don't see how the use of latches would do anything to increase the number of control bus lines.
 

ErnieM

Joined Apr 24, 2011
8,271
What are the " chips that can be controlled through tri-state logic "? What controls them, what inputs do the need, and what do they output?
 

Thread Starter

HalfMadDad

Joined Jun 10, 2016
43
What are the " chips that can be controlled through tri-state logic "? What controls them, what inputs do the need, and what do they output?
Thanks Ernie

Okay, here is an example. Let's say we have two eprom chips, each has a chip enable pin, 8 address pins and 8 data pins. We can set one of the chip enable pins to enable, send an address over the address bus and read the 8 data pins.

However our circuit does a lot more than this and if we say the two chip enable lines are part of the "control bus", we could quickly run out of CPU pins for it. This is where I typically see people using FPGAs to expand the control bus along with chips such as 3-8 line decoders for the address bus etc.

Perhaps I am mixed up about something, please set me straight. If some latch has 8 inputs and 8 outputs and it has it's own chip enable pin and the outputs maintain their state with chip enable disabled, then could we not use two or three of them, with shared inputs to gain more outputs? 3 chip enables + 8 data lines in for a gain of 3X8 lines out ?
 

Papabravo

Joined Feb 24, 2006
18,068
This is just abuse, it is perfectly fine to say nothing, you don't have to sink to this
Sorry you feel that way, but it was not abuse! You mistook my meaning. The intent was to say that a schematic diagram in place of a sentence, paragraph, page, or multiple pages of ANY words, not specifically the ones you chose, is preferable. This is an often repeated theme. Some people take heed and others continue along their chosen path.
 

Thread Starter

HalfMadDad

Joined Jun 10, 2016
43
Thanks ElectricSpidey !

I read data sheets that were similar to this but your sheet answers my question!

"""
That is ideal for driving high-capacitance loads, such as memory and address buffers"

"""

It is a normal thing to use this to expand address/control buses, now I can move forward.

Thanks again
 

drjohsmith

Joined Dec 13, 2021
376
Why an FPGA is at the basis of the question

FPGAs are cheap, small , low power
it cost money to have each type of device on a board,
BOM cost, as well as Place, inspect, etc,

Bottom line, the fewer the devices on a board , the more reliable and the lower the production costs per board

A latch system, or more probably register,
would need control logic to decode the address / CE for each register
This is easy to build into the FPGA

The FPGA makes a single device load on the bus,
whilst the multiple registers would add load, so could run slower / make more EMI,

FPGA also allows the designer to "make mods"
in old days.........
for instance, one had to be very careful about polarity of control signals in and out
if there was a mistake, or information was not as correct as it could be,
which with preliminary data sheets is fairly common
then a new board spin is needed,
FPGA is a o sh1T moment, and a quick re code.

FPGAs allow design / definition / data to move in parallel
you dont worry that every thig is tied down,

Hope that helps
 

Thread Starter

HalfMadDad

Joined Jun 10, 2016
43
Hi drjohsmith.

I believe everything you wrote but I think I will skip FPGAs for an easier start. Your explatation, negates my statement that other people are just using FPGAs to make it harder to copy, so that is helpful too.
 

MrChips

Joined Oct 2, 2009
25,918
It is not easy to follow what you are requesting.
We don't know the situation of the bus that you wish to expand.
Latches are not the usual device for this. I would think that 3-state bus receiver/drivers would be the proper device. Just guessing.

A circuit diagram of your situation would save a thousand words.
 

LesJones

Joined Jan 8, 2017
3,701
Using a shift register (Which is just a number of latches connected in a particular way.) is a another way of using latches for an output expander. You just need need two outputs (Clock and data.) to give up to a very large number of outputs. Like many things there is a tradeoff. It will slow the data down. It may be OK in some situations but not others. You would need to provide schematics and timing requirements to get a meaningful answer. You have not supplied enough information to fully answer your question.

Les.
 

Thread Starter

HalfMadDad

Joined Jun 10, 2016
43
Thanks MsChips.

I am pretty early in to this and i want to create several different things. My first goal is to use a parallel port to control home-brew electronics. I am thinking about using Ada from the desktop, it is awesome but it really needs a full OS or RTOS.

I will have limited lines with a parallel port and there will be lots of other problems.
 

Thread Starter

HalfMadDad

Joined Jun 10, 2016
43
Thanks LesJones

Yes, I really should put together even a basic drawing.

I will be well under 10mHz with everything and in a lot of cases in the kHz range with stepper motor control etc.
Shift registers sound like a good idea too, thanks
 

MrChips

Joined Oct 2, 2009
25,918
Thanks MsChips.

I am pretty early in to this and i want to create several different things. My first goal is to use a parallel port to control home-brew electronics. I am thinking about using Ada from the desktop, it is awesome but it really needs a full OS or RTOS.

I will have limited lines with a parallel port and there will be lots of other problems.
Basically, you are making general statements. It would be best to look at a specific requirement.
If you have a specific project in mind, provide us with the details and perhaps we may be able to guide you with solving those specific port limitations. There are more than one ways to skin a cat.
 

Papabravo

Joined Feb 24, 2006
18,068
What Mr. chips said in post #17!

After following the thread I'm beginning to have a bit more insight on your original question. It sounds like you used the term "bus expansion", when what you had in mind was I/O expansion. In particular you were not interested in:
  1. Expanding the number of address bits on a particular address bus
  2. Expanding the number of data bits on a particular data bus
  3. Expanding the number of devices on a particular system by adding more address decoding via decoder chips or an FPGA
I think that you may be interested in extending the number of directly controllable I/O lines on a device, that has a limited number of those directly controllable I/O lines. The answer is that you can use latches as part of the solution. In fact the shift register is the more common solution for inputs, and a shift register/latch combination is used for outputs. In this fashion you can extend the I/O capability of an 8-pin part to literally hundreds of I/O points if you so desire.

AFAIK there are no single COTS (Commercial Off The Shelf) devices that implement a bi-directional I/O port(s). You can of course make one but it takes multiple parts. This is one place where an FPGA might be helpful. It has the requisite "stuff" to build shift registers and they can communicate with bi-directional I/O pins. Very useful and flexible.
 

Thread Starter

HalfMadDad

Joined Jun 10, 2016
43
Basically, you are making general statements. It would be best to look at a specific requirement.
If you have a specific project in mind, provide us with the details and perhaps we may be able to guide you with solving those specific port limitations. There are more than one ways to skin a cat.
Will Do!
 
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