making counter using latches

Thread Starter


Joined Jun 18, 2013
hi all,
i was working in some digital design and got stuck in this question.

Q-> i have to make a 4 bit synchronous counter using latches(instead of flipflops) and i am not allowed to make flops using latch(the master slave circuit), if anyone has a solution please reply me soon.


Joined Mar 31, 2012
What do you mean by "if anyone has a solution please reply me soon"? Are you asking for someone to give you the solution, or just asking if someone has a solution so that you know it is solvable?


Joined Feb 24, 2006
You do it in the same way as with flip-flops. You decode the present state of the four outputs and use that to determine the next state and present that data to the input in advance of the edge (rising or falling) that latches the input to the output.


Joined Mar 31, 2012
I'm not sure I understand the constraint against using latches to make flip-flops. The counter is supposed to be synchronous, which means that there is a global clock controlling when the latches (at least those providing the output state) change. So you have excitation logic and a clock governing a latch -- isn't that pretty much what a flip-flop is? Note that I'm using the term "flip-flop" to mean what I think is meant by the OP, since it is actually a pretty ambiguous term.


Joined Dec 29, 2010
May be a dumb way. But would this work......?.

Rich (BB code):
         |                                                           |
          --> Latch  ->  adder  ->  Latch --+
                   ^                                    ^
                    |                                     |
Output from the 1st latch



Joined Mar 31, 2012
It will work provided the gating logic implements edge-triggered behavior (or appropriate master-slave behavior). If you enable one of the latches on the positive phase of the clock and the other on the negative phase, you should be able to get it to work, but consider what you have just done -- rearrange the drawing just a bit and you have two latches cascaded in a classive master-slave arrangement. But it would seem that this is specifically prohibited by the OP's description of the problem constraints.