Hey,

I am currently working on my thesis on designing a TDR instrument and was wondering if I could use the comparator ADCMP582 for pulse generation. The idea is that a step generator would be connected to the ADCMP582’s non-inverting input, and the inverting input would be connected to a voltage reference. All the comparator would do is speed up the rising edge of the step generator to roughly 30 ps.

The question I have is that I don’t know how to terminate the output of the pulse generator. The output uses LVPECL, which is differential, but I want a single-ended output.

Can I just connect the positive output (Q) and leave the inverting output (/Q) floating, or is there a special termination? I did try to search for an LVPECL/CMOS-TTL converter, but all of the “fast” ones are very expensive from what I found.

If anyone has any ideas for a better fast step generator, I am open to suggestions. I just need the rise time to be <100 ps because I want decent resolution.

Regards,
Domen

 

TDR instrument

Time-Domain Reflectometer

LVPECL/CMOS-TTL

generally slow

better fast step generator

Please define step generator. Draw a picture of the output you want.

Can I just connect the positive output (Q) and leave the inverting output (/Q) floating,

Terminate all ECL outputs. You don't have to use all of them.

ADCMP582

The inputs must be in the range of -2V to +3V. (assuming +/-5V supplies) What is the output voltage on the PECL ICs?

A schematic = 1000 words.

 

Time-Domain Reflectometer

generally slow

Please define step generator. Draw a picture of the output you want.

Terminate all ECL outputs. You don't have to use all of them.

The inputs must be in the range of -2V to +3V. (assuming +/-5V supplies) What is the output voltage on the PECL ICs?

A schematic = 1000 words.

Thank you for your advice, and sorry for the late reply.

I haven’t finished the entire schematic yet, but I can share an image of the pulse‑generation, output stage and sampling circuit section. The circuit is a work in progress so some detail will be changed, but the core concept is there. The decoupling capacitors are placeholders for now, I still need to determine their proper values.

The output of the step generator is terminated as shown in the datasheet. The voltage reference and DAC are used to set the minimum trigger‑voltage threshold. The ADCMP582 is triggered by an STM32H7. In this configuration I want to generate a voltage step so i can then sample the reflections from a coaxial cable. The step amplitude that I want is +1V and rise time of max 100ps this is equivalent to a frequency of 3.5GHz(I am aware that the ADCMP582 has a rise time of 37ps, but my sampler's max frequency will be 8GHz and so I can satisfy nyquist I need a sampling frequency 2x larger then the sampled signal.



This is a example of the pulse that i want to generate.

Step generator​

Output stage.​

Sampling circuit.
​

The generated voltage step is routed to a power divider, where the coaxial test cable connects to the SMA connector.
Both the incident pulse and its reflection are then sampled sequentially by the circuit above. The MCU sets a comparison voltage for the samples, then simultaneously triggers the incident pulse and its internal coarse time delay. The coarse delay extends the effective sampling window, compensating for the limited fine‑delay range provided by the SY89296U. When the coarse delay reaches its preset point, it activates the fine delay, which in turn triggers the ADCMP582 latch to capture the signal.
Based on whether the sampled signal is above or below the comparison voltage, we obtain a value for that specific time point. After N measurements, the full waveform is reconstructed.

Based on your advice, I terminated the unused output of the ADCMP582 that is responsible for step generation. I’m now using only the output required to produce the step. I also disabled the latch, since it isn’t needed in this application.

Again I am thank fill for you're advice and if there is any thing that need a more detail explanation or fixing pleas drop a comment.

Regards,
Domen

 

A SIMPLE TDR (Time Domain Reflectometer) can be assembled with a few TTL gates AND a Schottkey fast inverter, if an oscilloscope with adequate response is available.
The driving capability of an actual TDR Instrument will depend on what the application is intended to be.
It just came to me that probably you can simply leave the unwanted output is simply open circuited. Just a few minutes of experimenting should show if that causes any problems. It will probably be discussed in the manufacturers data sheet, as well. Component FULL data sheets,often hold a great deal of useful information.
Of course, with that impossible to read circuit drawing it is difficult to evaluate the actual circuit.

 

Hey,

I am currently working on my thesis on designing a TDR instrument and was wondering if I could use the comparator ADCMP582 for pulse generation. The idea is that a step generator would be connected to the ADCMP582’s non-inverting input, and the inverting input would be connected to a voltage reference. All the comparator would do is speed up the rising edge of the step generator to roughly 30 ps.

The question I have is that I don’t know how to terminate the output of the pulse generator. The output uses LVPECL, which is differential, but I want a single-ended output.

Can I just connect the positive output (Q) and leave the inverting output (/Q) floating, or is there a special termination? I did try to search for an LVPECL/CMOS-TTL converter, but all of the “fast” ones are very expensive from what I found.

If anyone has any ideas for a better fast step generator, I am open to suggestions. I just need the rise time to be <100 ps because I want decent resolution.

Regards,
Domen

there are two numberes to consider re speed on ttl to lvpecl.

the edge speed of the lvpecl is determined by output capacitance and termination resistance . this is in the ps region.

the time from a ttl level edge and the coresponding edge on the output is the chips propergation delay, this is typicaly a few ns

the current flow inside the chip is best to be kept symetrical thus use the same terminationnon both the + and - output .

remenber its a transmision line, so treat it acordingly

 

But also be sure to check the driver IC for overheating while driving the line. The load resistors are the critical ones. those 100 ohm ones are just for stabilizing, to be IN SERIES with the driven line.

 

Regarding LV pecl termination
This is a derivative of ECL
It's a current output , relying upon the termination resistors for the voltage.

Look here for the options on how to terminate

https://www.renesas.com/en/document/apn/828-termination-lvpecl

The basis is the driver's are intended to drive 50 ohm to Vterm .