Up for Review: Design Considerations for Digital VLSI

RK37

Joined Jun 26, 2015
677
Hi @amin k

I made a number of revisions. There are two remaining sections that I'm not sure about.

1. "Latency is the time needed for change in output due to change in input and is described by the clock cycle"

I'm not sure what you mean by "and is described by the clock cycle." Also, this implies that latency is relevant only to synchronous logic.

2. "Hold time is very important to solve because otherwise setup time cannot be fixed by reducing the clock after fabrication."

This seems rather unclear to me. Do you think you could clarify your point here?

Thanks,
Robert
 

WBahn

Joined Mar 31, 2012
25,090
There are a few items that should probably be discussed as they are at the same conceptual level as most of the article:

The issue of clock skew in large digital circuits and how it can be dealt with using clock distribution trees.

The dangers of using gated clocks in asynchronous LUT-based designs (such as most FPGAs).

The use of flip flops having negative hold times. I killed a chip because I ported it to a faster process and wasn't using such flip flops and the customer's lead time requirement meant that we couldn't verify the design beyond ensuring that the circuit topology was identical. They weren't pleased -- but we had warned them of the risks of not running all the sims and they accepted the risks with their eyes wide open. Fortunately the sims that I did while the chip was being fabbed revealed the issue and they had a heads up that the chips that they had just paid about $40k for were likely to be bricks suitable only for physically proving out their post-processing and packaging. It turned out that this very thing was what was driving their time schedules, so it was not a project killer for them (but it easily could have been). We had the new design fully verified and ready to submit if it turned out that the original chips did, in fact, not function so that we could submit them immediately. Sure enough, the very day that the chips arrived we were able to verify that they were not reliable and we submitted the new database that day.
 

amin k

Joined Oct 16, 2016
16
Hi Robert,
First of all, thanks for your notes.
1. You are right. there is an unclarity in the sentence. In my opinion by changing "is described by the clock cycle" to "it can be measured by time scales or a number of clock cycles in a synchronous circuit" the problem will be solved.
2. The sentence is wrong and should be "A setup time violation that occurs after the fabrication process can be avoided by reducing the clock frequency, however, a hold time violation can not get corrected if it occurs after the fabrication process."
 

amin k

Joined Oct 16, 2016
16
WBahn,
thanks for your comment. I agree that I missed the things that you said and I think they should be discussed too. I see two ways for adding them. First by adding them to this article which I think it's not a good idea because it will make the article very long. On the other hand, I can define another article as the next part. and in it, I can discuss the items you said and also other missing items like asynchronous design considerations and also different pipelining methods. What do you think is better? Robert, I would appreciate it if you help me here.
 

WBahn

Joined Mar 31, 2012
25,090
It could go either way. If you are up against a word-count limit (or goal), it might still be worthwhile mentioning them in passing as other issues that will be explored in a separate article.
 

RK37

Joined Jun 26, 2015
677
Thanks for your input here, WBahn.

Amin,

I revised the two sections mentioned above. I agree that the article would be quite long if you discussed the additional topics. I think it would be preferable to mention them in passing, as WBahn suggested. Just before the Conclusion section, you currently have the following:

"We can also employ asynchronous design techniques to address issues associated with multiple clock domains, but we will look at that in a future article."

This would be a good place to add a few sentences about these additional topics. If you can write something and then post it here in the forum, I will make corresponding revisions to the article and then move it to Ready for Publication.
 

amin k

Joined Oct 16, 2016
16
Hi Robert,
Thanks for the revision.
The sentence you've mentioned should change to
"We can also employ asynchronous design techniques to address issues associated with multiple clock domains, but it may make the article longer. Therefore, we will cover this and other important materials such as the clock skew and its effects on the design and necessity of using clock trees in FPGAs, gated clocks and their problems and etc in the next article."
 
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