Hi everyone,

I am currently working on a high-power half-bridge converter project and would like to get some professional feedback on my gate driver stage design. I'm an Automation Engineering student at UNETI and this is my first time handling such high gate charges at this frequency.

Design Context:

• Power Stage: Half-bridge configuration.
• MOSFETs: IRFP260N (TO-247) - Q_g approx 234nC to $240nC.
• Switching Frequency: 100kHz.
• Target Load: Approx. 1.2kW (Continuous current around 20A, peaking at 50A).
• Driver IC: UCC21520 (Isolated Dual-Channel).

Gate Drive Strategy:

• Isolation: Fully isolated control side (3.3V MCU logic).
• Bias Supply: Using B1212S-2W isolated DC-DC converters to provide a floating bias for each high-side and low-side switch.
• Drive Voltage: +15V for the gate-source voltage.

I have a few specific concerns regarding long-term reliability:

1. Gate Drive Power Dissipation: At 100kHz and Q_g = 240nC, the calculated power dissipation inside the UCC21520 is nearing 0.7W - 1W. Given the small package, should I be worried about thermal runaway during extended operation?
2. Buffer Stage: Would you recommend adding an external buffer (like the ZXGD3006 or a discrete Totem-pole) to offload the heat from the UCC21520 and ensure sharper switching edges?
3. Floating Supply Stability: How reliable is the B1212S in a 100kHz environment? Should I add specific LC filtering to the output of these DC-DC modules to handle the high dv/dt transients at the switching nodes?
4. Layout Advice: For 20A continuous operation, are there any pitfalls I should avoid regarding the Kelvin source connection and common-mode transient immunity (CMTI) for this IC?

I've attached my current schematic and PCB footprint for your review. Any advice on gate resistor optimization or thermal management would be greatly appreciated.
Here the schematic


Best regards,

Duong

 

On the Gate Driver you have 10uF and 100uF caps. I don't know how good the 10uF is at high frequencies. Look at the data sheet for the Driver and see what they want. They might want a small, high frequency cap right on the pins of the IC.

I have never put a cap on the Gate-Source of a MOSFET.

Why is the schematic symbol for IC1 not the same as IP1, 2? It hurts my head to see the IP1 area up-side-down.

 

Thanks for the feedback.

Regarding the decoupling capacitors: the 10µF is currently a general-purpose capacitor, but I agree it may not perform well at high frequency. I will check the datasheet of the gate driver (e.g. UCC21520 gate driver) and add a small high-frequency ceramic capacitor (e.g. 100nF) placed as close as possible to the IC supply pins for proper decoupling.

About the gate-source capacitor: this capacitor is not part of the default design. It was added as an optional footprint so that it can be populated if needed during testing to help reduce noise or slow down switching (e.g. mitigate ringing/EMI). I understand it’s not commonly used and will only be populated if measurements justify it

For the schematic symbol orientation: agreed, the inconsistency between IC1 and IP1/IP2 makes the schematic harder to follow. This mainly comes from my current drafting stage and lack of experience in schematic organization. I will clean this up and keep a consistent orientation for better readability.

 

I suggest a careful reading of the data sheets for the drivers. Especially the power dissipation max values. You might be OK there, or maybe not.

 

I am not a pro at all, but just out of curiosity, how did you pick 100kHz for the frequency??