Unable to solve this practice problem can somebody help me out plz

WBahn

Joined Mar 31, 2012
25,776
This is not Homework Done For You. Please show your best attempt to work the problem as far as you can. That will help identify where you are getting stuck so that we can help you get past that spot so that you can continue making progress.
 

ci139

Joined Jul 11, 2016
1,464
the effect of D on the \10/ thingy is undefined ? does it invert on D=HIGH or D=LOW
moslt likely it's a 2MUX and (i speculate) the \10/ are input addresses ... maybe -- thus D is actually an address input and that very thing generates a conflict ... guessing the right function ?
 

WBahn

Joined Mar 31, 2012
25,776
the effect of D on the \10/ thingy is undefined ? does it invert on D=HIGH or D=LOW
moslt likely it's a 2MUX and (i speculate) the \10/ are input addresses ... maybe -- thus D is actually an address input and that very thing generates a conflict ... guessing the right function ?
It's the standard symbol for a 2:1 Mux. D goes to the input-select pin. When D is 0 the output is equal to the input on the '0' line and if D is 1 then it's equal to the output on the '1' line.

How does that generate a conflict?
 

ci139

Joined Jul 11, 2016
1,464
How does that generate a conflict?
? a DATA signal going to ADDRESS input line ? . . . which creates up a little confusion as -- what is the "actual" input pin functional assignment ... as the D is also going to C₀ . . . (so D=A=C₀ ... ? which one - if any - is it ...)
 

Analog Ground

Joined Apr 24, 2019
397
I think you are over thinking the problem. The inputs are not DATA or ADDRESS. They are just inputs. D is an input to the function which goes to the carry input of the first 1 bit full adder AND the Select input of the four 2:1 mux. There is no "conflict". The problem simplifies everything by setting B0, B1, B2, B3 and D to "1". Start by thinking, "If these inputs are set to "1", how does the output of the first full adder change if A0 changes". Look up the truth table for a 2:1 mux and a full adder. Start simple.

Edit: This is not a "trick" problem. The function of the circuit has a particular purpose and can be quickly recognized by someone with more experience. Go for it! Hint: A3, A2, A1, A0 is a binary number and B3, B2, B1 and B0 is another binary number.
 
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WBahn

Joined Mar 31, 2012
25,776
? a DATA signal going to ADDRESS input line ? . . . which creates up a little confusion as -- what is the "actual" input pin functional assignment ... as the D is also going to C₀ . . . (so D=A=C₀ ... ? which one - if any - is it ...)
D is not a data line, it is a control signal. This is the classic configuration to implement two's complement subtraction using a binary adder.
 

ci139

Joined Jul 11, 2016
1,464
D is not a data line, it is a control signal.
( oh boy ... oh boy ... oh boy)
"obviously" . . . if so comes . . . i've been made hypersensitive to such by all sort of miss references for pin functions on various datasheets
quite common is to miss reference (read "label inadequately") the polarity and function (active edge / active level) of the CLK inputs
http://www.circuitstoday.com/triggering-of-flip-flops
example :
for https://www.ti.com/lit/ds/symlink/sn54s194.pdf?ts=1591479735393&ref_url=https://www.ti.com/product/SN54S194
it's simulated according to the schematic on the d/s . . . i still don't know how the real chip interprets the S0 S1 inputs ??? (all cool)
simplifiedLogicTEST-0200_Verif-2.gif
 
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WBahn

Joined Mar 31, 2012
25,776
( oh boy ... oh boy ... oh boy)
"obviously" . . . if so comes . . . i've been made hypersensitive to such by all sort of missreferences for pin functions on various datasheets
example :
for https://www.ti.com/lit/ds/symlink/sn54s194.pdf?ts=1591479735393&ref_url=https://www.ti.com/product/SN54S194
it's simulated according to the schematic on the d/s . . . i still don't know how the real chip interprets the S0 S1 inputs ??? (all cool)
View attachment 209057



The real chip interprets the input just like the data sheet states, both in the descriptive text and the function table.

If the \CLR is HI, then the S1,S0 bits control the mode. If both are LO, then shifting is inhibited. If both are HI, the data on the parallel inputs is loaded on the rising clock edge, if S1=LO and S0=HI, then data is synchronously shifted to the right with new data taken from the SERIAL RIGHT input, while if S1=HI and So=LO, then data is synchronously shifted to the left with new data taken from the SERIAL LEFTinput.

What else is there to understand?
 

Analog Ground

Joined Apr 24, 2019
397
( oh boy ... oh boy ... oh boy)
"obviously" . . . if so comes . . . i've been made hypersensitive to such by all sort of miss references for pin functions on various datasheets
quite common is to miss reference (read "label inadequately") the polarity and function (active edge / active level) of the CLK inputs
http://www.circuitstoday.com/triggering-of-flip-flops
example :
for https://www.ti.com/lit/ds/symlink/sn54s194.pdf?ts=1591479735393&ref_url=https://www.ti.com/product/SN54S194
it's simulated according to the schematic on the d/s . . . i still don't know how the real chip interprets the S0 S1 inputs ??? (all cool)
View attachment 209057
In the 74 series parts, there *tends* to be common signal names. However, in this case of an adder, look at the 74283 where the inputs are Ax, Bx and the outputs are Sigma or S. These are the names in the TS circuit which is a special adder. I don't know where the "D" input name comes from. So, the names are conventional for the type of function. Of course, if you don't recognize the function, this is not much help! If it is any consolation, two's complement binary arithmetic is complicated. The general topic then includes ones complement and sign + magnitude arithmetic. It all gets fairly advanced and easy to forget.
 
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WBahn

Joined Mar 31, 2012
25,776
If it is any consolation, two's complement binary arithmetic is complicated. The general topic then includes ones complement and sign + magnitude arithmetic. It all gets fairly advanced and easy to forget.
Two's complement is very straight forward. From the definition of Radix-B Complement for an N-digit representation:

-x = B^N - x

In the case of an N-bit binary representation

-x = 2^N - x

There's really not much more to it, though there are some common tricks that fall out directly from it, such as

-x = [(2^N - 1) - x] + 1

The, recognizing that (2^N - 1) is a pattern of all 1s and that subtracting a 0 from a 1 leaves a 1 while subtracting a 1 from a 1 leaves a 0, we have

[(2^N - 1) - x] = ~x (where ~x is the bitwise negation of x)

yielding

-x = ~x + 1

which is the common trick that to take the two's complement of a value you flip all the bits and add one.

It's this trick that is at the heart of the circuit the TS posted in which the control signal also serves to provide the +1 via the carry in bit to the adder.
 
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