hai,

i had been to hardware designing for past few years.Presently i am designing an inverter.Our inverter is a solar based one.To describe my circuit shortly,

in my circuit i have a full H- bridge to convert dc signals upto 350v to ac.I have designed it in such a way that the two high sides are being driven by the FAN73711 ic and low sides by IX4427.Presently we are applying SPWM in the high side and normal square pulses at the corresponding low side of the bridge.even though i had placed N-Mosfets in my circuits, later i replaced them with IGBTs from STMicroelectronics.At the first i drove a half cycle by applying around 200V dc across the drains of the high side mosfets and got a good output .....half cycles of ac.later i drove the other half cycle and got a similar result.but later i integrated the two half cycles and tried to drive the bridge.but unfortunately i am just able to reach 30v dc which i supply to the h-bridge for the ac convertion from my variable power supply .....after 30v i started hearing noise from my dc-dc power supply.On probing my gate signals i found noise in my gate signals.Doubting the power supply adapter, the changed my twelve volt adapter and powered my board from a battery(12v).But found similar issue there too.What could be the possible reason behind the noise in the gate signals.I am sure that only because of the noise in the gate signals i am not able to properly drive my bridge..What could be the possible reason behind.please note that in the schematics attached by me, the gate drivers aren't driven by the 20v instead ,are driven by +12V power supply.can anyone please help me regarding this......

 

Curious, how do you insure there is dead time between high and low side driver ?

Regards, Dana.

 

i have given almost 2ms dead time.

 

Noise on gate signals inductive looking, ringing ? Can you post a screenshot
of gate signal, at MOSFET gate pin ?

The Gate drive Rs, 2.2 ohms, look a little low, I am more used to seeing 10 ohms
or more. Grounding and pcb layout very important to minimize L effects. Split
grounds to handle high bridge current flowing do not ground bounce logic circuit
grounds......

https://www.infineon.com/dgdl/Infin...N.pdf?fileId=5546d462518ffd8501523ee694b74f18

https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=4&ved=2ahUKEwiRrL_o6-TcAhXkQd8KHWWeCZ8QFjADegQIBxAC&url=https://toshiba.semicon-storage.com/info/docget.jsp?did=59460&prodName=TK5Q65W&usg=AOvVaw3FqZTL5ilAhu1PJcvSksZv

Bypass cap technology also important.



Regards, Dana.