TX FIFO and RX FIFO in Network Controller

shteii01

Joined Feb 19, 2010
4,644
TX holds bits to be transmitted out.
RX holds received bits that need to be read by the device.

Both are temporary storages and not meant to be used to store important program data.
 

Thread Starter

DragosAlbu

Joined Jan 8, 2017
14
TX holds bits to be transmitted out.
RX holds received bits that need to be read by the device.

Both are temporary storages and not meant to be used to store important program data.
But do you know how the parallel bits are taken from the bus and are put in the TX FIFO? Please if you can help me with this information.
 

Papabravo

Joined Feb 24, 2006
16,519
I believe the serialization of the parallel data in the TXFIFO takes place when the data is removed from the TXFIFO and placed into the TX SHIFT REGISTER. Similarly on receive the bytes(words) are assembled in a serial to parallel shift register and placed in the RXFIFO once the appropriate boundaries are recognized.
 

Thread Starter

DragosAlbu

Joined Jan 8, 2017
14
I believe the serialization of the parallel data in the TXFIFO takes place when the data is removed from the TXFIFO and placed into the TX SHIFT REGISTER. Similarly on receive the bytes(words) are assembled in a serial to parallel shift register and placed in the RXFIFO once the appropriate boundaries are recognized.
Do you know where can I find a better block diagram including the TX SHIFT REGISTER?
 

Thread Starter

DragosAlbu

Joined Jan 8, 2017
14
Hello,

The following PDF will show you the ethernet theory of operation.

Bertus
Thank you...but there's a lot of technical stuff for me....I'm studying Computer Science not Electronics....so I am trying to find something easier to understand.
 

Papabravo

Joined Feb 24, 2006
16,519
Thank you...but there's a lot of technical stuff for me....I'm studying Computer Science not Electronics....so I am trying to find something easier to understand.
Not to sugar coat this topic but you can't expect to dive into something of this complexity (run a marathon) without first learning to crawl and walk. So why don't you slow down, divide, and conquer.

Here are some datasheets for basic MSI parts:

The one with the serial output would be used in the transmitter. the one with the serial input would be used in the receiver. Notice how the serial ouput changes regardless of weather the register was "loaded" or "shifted". Here is a thought exercise:

If the data has to be shifted out LSB (Least Significant Bit) first -- how could you arrange for that to happen?​
 

andrewmm

Joined Feb 25, 2011
1,645
small question, long answer ..

How much detail do you want ?

top level, ethernet is split into layers, as per the OSI model.

Layer 1 is the physical,
the cable and driving,

generally its considered they layer one is responsible for handling all the Ethernet electrical and ns by ns timing, and the interface to layer two is parallel,

i.e the layer one does the parallel to serial and back conversion and has the first / last fifos in.

Having said that, the picture shows the fifos onto the cpu data bus,

Which implies the fifos are not at level 1, but higher up ,
The NIC does many things.


You could be suffering the old problem of students,
the answer depends not upon the question but what the question setter wants.

i.e. if you ask "why are days warmer then nights" to a phd student and to a 5 year old you would expect different answers.
 
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