But do you know how the parallel bits are taken from the bus and are put in the TX FIFO? Please if you can help me with this information.TX holds bits to be transmitted out.
RX holds received bits that need to be read by the device.
Both are temporary storages and not meant to be used to store important program data.
Do you know where can I find a better block diagram including the TX SHIFT REGISTER?I believe the serialization of the parallel data in the TXFIFO takes place when the data is removed from the TXFIFO and placed into the TX SHIFT REGISTER. Similarly on receive the bytes(words) are assembled in a serial to parallel shift register and placed in the RXFIFO once the appropriate boundaries are recognized.
Not to sugar coat this topic but you can't expect to dive into something of this complexity (run a marathon) without first learning to crawl and walk. So why don't you slow down, divide, and conquer.Thank you...but there's a lot of technical stuff for me....I'm studying Computer Science not Electronics....so I am trying to find something easier to understand.
FIFO, First In, First Out register array. Bytes are stuffed in one after another and read out in the same sequence. Check out a FIFO data sheet. 74LS224 for instance.
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by Jake Hertz