So, I'm trying to solve a question about a TTL Gate, but I'm kinda stuck.

I have this circuit:

And I only have to answer if the diodes and transistors are ON or OFF.
But I'm not sure what T3's behaviour would be when, let's say, e1 is low and e2 is high, since both T1 and T2 are connected to T3.

Can somebody help me, please?
Thanks in advance.

 

T1 and T2 are in parallel. Since T1 is OFF you can ignore it. T2 being ON overrides any effect of T1.

If T2 is ON, is T3 ON or OFF?

 

So T3 will be ON, right?
That's what I thought too, but then I saw this on the site:

And it said:

Notice how transistors Q3 and Q4 are paralleled at their collector and emitter terminals. In essence, these two transistors are acting as paralleled switches, allowing current through resistors R3 and R4 according to the logic levels of inputs A and B. If any input is at a "high" (1) level, then at least one of the two transistors (Q3 and/or Q4) will be saturated, allowing current through resistors R3 and R4, and turning on the final output transistor Q5 for a "low" (0) logic level output. The only way the output of this circuit can ever assume a "high" (1) state is if both Q3 and Q4 are cutoff, which means both inputs would have to be grounded, or "low" (0).

This got me confused.
Ooh, I think I understand it now. Q5 will be turned on, but since it's a pull-down transistor, the output will be low.
Is that it?

 

For reference, that's not a TTL gate, it's a diode-transistor gate (DTL).

 

Oh, I forgot to thank you.

Thank you, @MrChips


@crutschow : I see, thanks for correcting me.

 

In your second example, Q5 is called open-collector output. The output needs a pull-up resistor in order to present a proper LOW/HIGH logic output.