Trouble with 2 outputs feeding 1 input

Deleted member 115935

Joined Dec 31, 1969
0
You have a few problems,
This is very similar to one of the schematics we used to use in interviews,

first the 393 counter, has an asynchronous clear. Any pulse high will clear counter.
the clr is driven by an and gate, driven by the Q outputs of the counter. The Q outputs will not be aligned, rise time is different to fall time, so you will get glitches that will clear the counter when you are not expecting.

second your using the same 'glitchy' output, to drive the clock input of a counter,
so the following counter will also count when you are not expecting.

Look at counters such as the 163 , and use the synchronous load, not the asynchronous clear.

Looking at the switch, what are you expecting that to do ?
the rc circuit you have is a sort of power on reset circuit. Are you aiming to de bounce the switch ? That it will, but it will also mean after you let go of the switch, there will be a delay, in which time another clock pulse could come in and move the counter on.

The diode OR gate. Diodes are ok to use, but you need negative logic.
search diode transistor logic,
 
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