Hi,
This is a nagging problem with my version of a classic binary clock. It comes with all the baggage expected of an old project built with older tools, but here's what I have: My version of a design off the web uses 74393 counters to set up seconds, minutes and hours, with logic to clear each as appropriate and clock the next counter in the sequence. It works just fine until I try to implement the part that sets the minutes and hours. Here, it uses a debounced switch to enable the clock pulse to feed directly to the minutes counter input when pressed, without disconnecting that input from the output of the previous counter. A couple of diodes are supposed to take care of keeping the pulses positive coming from either output, and a resistor to ground pulls the input down if both outputs are low. Doesn't work. I'm confident counter B is counting, but when I put in the diode from its CLEAR over to C, the pulse isn't coming through. The min set module is working fine. When enabled, the minutes counter counts at 1 Hz. But nothing moves when set is not enabled.
Ideas about things that can be going wrong? My background is weak on theory, but I've dabbled for many years.
Note, I'm using LS393's, not HC393's.

Attached is a piece of the schematic showing the B counter feeding the C counter, with the min set module also feeding the C counter. Other stuff cut out for simplicity.

Thanks for any thoughts. Tim

 

I would make sure both diodes check good and installed with the correct polarity. If the B counter is counting correctly you should see a pulse on the output at pin #6 of the 7408 every 60 seconds.
SG

 

Your schematic is mixing parts from several different logic families. It's usually best to stick to a single family unless there's a darn good reason not to.

A likely cause is that the output of TTL logic doesn't go to the positive rail to begin with. You are Vcc is 5 V then your HI level output is likely in the 3 V to 3.5 V range. Drop that by a diode drop and you are getting close to, if not in, no-man's land. Add to that the 10 kΩ pull down and there's a good change you are at a level that can't be recognized as a HI.

Hold the inputs to the AND gate near B HI (disconnect from the counter) and measure the voltage at the CLK input to C. What is it?

 

I would make sure both diodes check good and installed with the correct polarity. If the B counter is counting correctly you should see a pulse on the output at pin #6 of the 7408 every 60 seconds.
SG

Yes, the diodes test ok, and gave interesting results when inserted backwards, but are inserted correctly, but the output from the 7408 is not going past the diode. It functions fine in absence of the diode and the whole min set module.

Any suggestions how to check for the pulse on the output of the 7408? It seems to be very fast... presumably the rise time of the high state, which is then cut off by resetting the counter? nsec? I can see the pulse when it clocks the next counter, but I can't see it on my DVM (refresh rate is msec), and my very primitive Scope has no memory function to capture a fleeting trace.

 

Your schematic is mixing parts from several different logic families. It's usually best to stick to a single family unless there's a darn good reason not to.

A likely cause is that the output of TTL logic doesn't go to the positive rail to begin with. You are Vcc is 5 V then your HI level output is likely in the 3 V to 3.5 V range. Drop that by a diode drop and you are getting close to, if not in, no-man's land. Add to that the 10 kΩ pull down and there's a good change you are at a level that can't be recognized as a HI.

Hold the inputs to the AND gate near B HI (disconnect from the counter) and measure the voltage at the CLK input to C. What is it?

I agree about mixing parts from the parts box. The schematic I posted was the one I'm using as a guide. The parts currently on the board are actually 74LS393N, SN74ALS08N, and a CD40106BE, that I'm using to debounce the switches.

With the 7408 inputs at +4.97 V, its output is 3.5V, and the diode takes it down to 2.95 V at the CLK input to C, in the presence of the 10K resistor. So I guess technically, it should still be high. But is the AND pulse too narrow? Maybe excess capacitance is preventing the pulse from reaching the threshold where the falling edge triggers the C counter (?) I can see the clock signal I'm using on my DVM, but I can't see the pulse from the AND gate because it gets reset fast (how fast? 50 nsec?).
Thanks

 

I agree about mixing parts from the parts box. The schematic I posted was the one I'm using as a guide. The parts currently on the board are actually 74LS393N, SN74ALS08N, and a CD40106BE, that I'm using to debounce the switches.

With the 7408 inputs at +4.97 V, its output is 3.5V, and the diode takes it down to 2.95 V at the CLK input to C, in the presence of the 10K resistor. So I guess technically, it should still be high. But is the AND pulse too narrow? Maybe excess capacitance is preventing the pulse from reaching the threshold where the falling edge triggers the C counter (?) I can see the clock signal I'm using on my DVM, but I can't see the pulse from the AND gate because it gets reset fast (how fast? 50 nsec?).
Thanks

Well, those are the kinds of gremlins that you let out of the box when you choose to use asynchronous logic and ad hoc wired-OR designs with mixed-logic families.

Why not use a fully synchronous design?

 

It would be nice if the schematic you posted reflected the circuit you are asking us to diagnose. For example, 10K is an adequate resistor value to pull down a CMOS input stage (post #1) (although it is a bit too large from a noise control perspective), so there is no reason to consider it - except that the chip is not CMOS (post #5).

10K is too large to pull down an LS gate input and way too large for standard TTL. For LS, the calculated max value for pull down is 2K (0.8 V / 0.4 mA). 1K is tolerable, 470 is a much more often used value. For TTL, 500 calculated, 100-220 normal.

ak

 

I'm still new here, so I could be way off base... but is the pull-down resistor even needed here? Doesn't the output of the AND gates hold the input low at the appropriate times? Or does the presence of the diodes change that? Otherwise, I agree, 10k for a pull-down seem too much.

Does you clock pulse have the option to slow down, or single-step? If not, you might consider adding that, just for debugging purposes, of course.

 

Why not use a fully synchronous design?

Well, sometimes you gotta walk before you can run, no?

My first clock will probably be an asynchronous design too, maybe.

 

Deleted. I thought you wanted to reset the counterto zero.
Les.

 

is the pull-down resistor even needed here?

Yes.

Doesn't the output of the AND gates hold the input low at the appropriate times?

No.

Or does the presence of the diodes change that?

Yes.

A TTL input is a current *source*. You have to pull it low by providing a current path to GND, and sink enough current for it to notice. With no path to GND, a TTL input floats high enough to be a logic 1. So if the counter input is at about 1.8 V and the AND gate output is at 0.1 V, the diode is reverse biases and the gate output is not sinking any current from the counter input.

ak

 

A TTL input is a current *source*. You have to pull it low by providing a current path to GND, and sink enough current for it to notice. With no path to GND, a TTL input floats high enough to be a logic 1. So if the counter input is at about 1.8 V and the AND gate output is at 0.1 V, the diode is reverse biases and the gate output is not sinking any current from the counter input.
ak

OK, I had a feeling that the resistor values were an issue, but I hoped the design would not critically depend on the exact device. If I go with 1K or 470 on the pull-down, then the pulse coming to the CLK of the downstream counter may never get above LS TTL nomans's land. I'll test it when I get a chance to see if maybe there's a balance I can strike. Probably why the original designer of the thing used the CMOS version, 74HC393. Mouser has some nice CD74HCT393E counters for sale...

Thanks for the reality check, Tim

 

The (not so) easy answer is to replace the diode-OR circuit with an actual OR gate...

ak

 

The (not so) easy answer is to replace the diode-OR circuit with an actual OR gate...

ak

I had just that thought earlier, when it occurred to me that an or gate would, both, pass clocking pulses through at a reasonable high V, and go properly low between pulses.

Would you judge that if I went with all HCT-type devices with the existing design, prospects would be better? Outputs should be running higher high levels and slightly lower lows?
Tim

 

HC or HCT, but don't mix the two.

ak

 

Don't mix families!

If you want an OR function, use an OR-gate.
In a pinch, you can use diodes and resistors but avoid it if you can.

 

OK, I had a feeling that the resistor values were an issue, but I hoped the design would not critically depend on the exact device.

Have you measured the voltage across the 10K when the outputs of the 7408 are low? If it's below 1 volt the 10K should be OK.
SG

 

The (not so) easy answer is to replace the diode-OR circuit with an actual OR gate...

Exactly what I was thinking.

It's been a long while since I've messed with logic, but it seems intuitive that a 2 IN OR gate would suffice. However AnalogKid says it's not so easy a solution, I don't know why. I'm not disagreeing, just saying I personally don't understand what would be so difficult about it.

 

However AnalogKid says it's not so easy a solution, I don't know why. I'm not disagreeing, just saying I personally don't understand what would be so difficult about it.

As far as showing on the schematic nothing. May not be easy if trying to incorporate into an existing circuit. I can see a couple reason why they would used diodes. I can't see the entire circuit so maybe only one OR gate was needed and the designer didn't want to see three unused gates or maybe the PCB layout was an issue.
SG

 

As far as showing on the schematic nothing. May not be easy if trying to incorporate into an existing circuit. I can see a couple reason why they would used diodes. I can't see the entire circuit so maybe only one OR gate was needed and the designer didn't want to see three unused gates or maybe the PCB layout was an issue.
SG

That could be. I also see the usefulness of the two diodes. My concern about them is the voltage drop across them. May not be significant, but it's possible (at least in my mind) that they could affect how the circuit works. HOWEVER, the circuit seems to work through the first diode, the upper one, so maybe I'm wrong. But like I said, it's been a long time since I've messed with logic.