ah, i just love your posts. They are different from others. They give me an urge to study more.

 

Annoyance? Couldn't the same be said for Vbe? An ideal p-n junction in the forward direction has zero voltage drop for any finite current value. Second, the current controlling Ic is emitter current Ie, not base current Ib.

Thirdly, base current may not contribute directly to Ic, but it has a useful purpose. Every bjt can be fabricated for "supergain" behavior, beta value can be 4,000 to 5,000 typically. The base current exists due to hole density in the base. When b-e junction is forward biased, holes drift from base to emitter, recombining w/ emitter electrons.

The value of this hole drift is determined by the density of acceptor atoms which is controlled during the fabrication process. A sparse acceptor density & very thin base region results in great current gain values, beta. But designing the device for superbeta performance involves tradeoffs.

With thin base dimensions, & sparse acceptor density in the base, Vce blocking capability is low, & collector to base leakage current is high. Leakage from collector to base is very undesirable, it hurts performance while providing no benefit. Also, punch through when Vce breakdown occurs is very undesirable.

So how we avoid these 2 bad behavior issues, is to increase doping density of acceptor atoms in the base region (npn device), which reduces c-b leakage current, & widen base region, which increases Vce blocking ability. The price paid is lower beta & higher base current, but it is worth it. Again, Ib does not directly contribute to Ic, but it mitigates these 2 problems I discussed.

I would rather have a bjt that required a little more base current but exhibits less c-b leakage, as well as not exhibit Vce punch-through. I'm sure you don't want those either.

Likewise, Vbe is an annoyance. In logic, output swing for an emitter follower cannot go to the rail because of Vbe. If Vbe were 0.01 V, life would be better. A power amplifier exhibits crossover distortion because of Vbe value of 0.7V. If it were 0, crossover would have lower distortion.

Germanium bjt devices have lower Vbe, a desirable feature. But their collector-base leakage current is much greater than silicon, esp at high temp. With Si, we accept the higher Vbe in return for better c-b leakage current values. It's a tradeoff indeed.

Finally, if a bjt amp stage is configured as an emitter follower, a common use, Ib combines with Ic & Ie is the load current. In an EF, Ib is not going to waste, it drives the load. Many standard npn linear regulators use an EF stage for the output. The low dropout regulators use either a pnp bjt or P MOSFET stage. The configuration is common emitter or common source. With CE, Ib does not drive the load.

Anyway, I had to clear up this urban myth that Ib is just an annoyance. I studied semiconductor physics including fabrication, & believe me, if we have had the ability to produce bjt parts with beta of 5,000 since the 60's, but we generally opt not to, you know there is a good reason. If higher base current was merely an annoyance, it would have been reduced in every device to the extent feasible.

OEM producers of bjt intentionally lower beta, & increase base current, because there is something to be gained by doing so. Higher acceptor atom density reduces c-b leakage, & longer base region distance increases Vce blocking value. These are good things - I'm sure you would agree. BR.

Claude

You ignored the context of my comment about Ib being an annoyance. Here's what I said:

Differential amplifiers, the heart of op amps, are basically (IMHO) voltage-controlled devices. The base current is an annoyance that has to be dealt with, or at least accounted for.

In op amps, Ib is an annoyance.
Why can't we just say that CB leakage is also an annoyance?
And I don't agree that Ib driving the load in an emitter follower is a plus. In most usages of emitter followers, the goal is to reduce loading on the source. Ib loads the source.

Maybe they should start adding gate current to FETs. Think of all the advantages.

 

You ignored the context of my comment about Ib being an annoyance. Here's what I said: In op amps, Ib is an annoyance.
Why can't we just say that CB leakage is also an annoyance?
And I don't agree that Ib driving the load in an emitter follower is a plus. In most usages of emitter followers, the goal is to reduce loading on the source. Ib loads the source.

Maybe they should start adding gate current to FETs. Think of all the advantages.

I just explained that in op amps, superbeta devices are used in front end to minimize Ib. The input to an op amp need not withstand high Vce values. The leakage current c-b is minimized by a servo loop that forces Vbc to near zero volts. Just as Ib can be regarded as an annoyance, so can Vbe & Vbc.

For an op amp, why not germanium input pair of bjt? Vbe is lower, resulting in lower output errors due to input voltage offset. The answer is increased leakage current, also an annoyance. We accept a higher Vbe, one form of annoyance, in return for lower c-b leakage current.

If both bjt parts had zero Vbe, they would be perfectly Vbe matched, hence the output error due to input Vbe offset would be zero. But real world op amp input bjt pairs have an error due to non-zero Vbe which do not perfectly match. Likewise, if Ib were zero, the mismatch in Ib values is zero, as is the output error due to Ib mismatch.

Ib & Vbe ideally vanish, if we could have that. But we cannot. My wishing that Vbe and/or Ib vanish does not make it happen, so I deal with both of them, knowing the tradeoffs involved. Again, of course it would be great if Vbe & Ib both were smaller, but for now, I use what is available.

Regarding Ib loading the source, that is true, but nonetheless, the current provided by the source does power the load, a desirable thing. Compare an EF w/ a CE output stage. Both load the source. Both demand a current from the source. For CE, the base current is Ic/beta. But for EF, said Ib is Ie(beta+1). The "+1" is not very significant for large beta values, but for high current devices, where the operating current is large, beta may be under 10, or even 5. Although we wish to minimize the current demanded from the source, it must provide the needed base drive.

At least w/ an EF, that base drive is going to power the load. That is my point. We desire to minimize it, we do so the best we can, but the final result is that w/ a CE the base current is lost, with an EF it drives the load. I don't see how that can be contested.

"Annoyance" is very subjective. I could claim that an ideal device amplifies a signal in either current or voltage form, w/o any Ib, Vbe, Vbc, or Ie. If a signal is amplified by a bjt, & all those parameters vanish, the device dissipates zero power! Hence any quantity other than Ic can be called an annoyance.

Why don't we add gate current to a FET? Because nothing is gained, at least as far as conduction current goes. But making the g-s capacitance larger increases gm, the transconductance (id/vgs). So we are in fact adding current to the gate. Another classic tradeoff. Increasing gm results in more g-s capacitance, & more gate current. Some applications favor this, some do not.

The FET & bjt are so well analyzed for so long, critics who say opposite to the OEM, are easily demolished. If Ib, Ig, etc., was a mere annoyance, every device would have these quantities minimized 100%. The fact that devices are deliberately produced having larger Ib & Ig than what is the minimum attainable, is because something else is gained.

There is a tangible benefit to making a bjt which requires more Ib than what is the minimum value attainable. It's a tradeoff. I will concede on the following. If we can reduce Ib, Ig, Vbe, Vgs, etc. without degrading another important parameter, I say we should do so. Of course if I'm driving a 5 amp motor with a bjt, I would much rather have a beta of 50 vs. 25. A value of 100 is better yet, heck, I'd love a beta of 1,000, or higher.

But reality is that my c-b leakage current would be atrocious, as well as my Vce blocking capability. If the motor is 24V, I need at least 30V, better yet 40V Vce to insure against punch through.

Extra base current is NOT an "annoyance" if it means I avoid punch through. How can you say Ib is an annoyance, when without it you would get punch through? Anybody who knows anything knows that punch through is MUCH MORE ANNOYING than Ib. Seriously is that even open for debate?

Claude

 

Thanks for the core dumps.

Why don't we add gate current to a FET? Because nothing is gained, at least as far as conduction current goes. But making the g-s capacitance larger increases gm, the transconductance (id/vgs). So we are in fact adding current to the gate. Another classic tradeoff. Increasing gm results in more g-s capacitance, & more gate current. Some applications favor this, some do not.

Apparently you don't recognize sarcasm. I even added rolled eyes after my question about adding gate current to FETs, to signify such.

To a semiconductor physicist or design engineer, Ib is apparently a useful tool.
I don't think you will ever find a board-level circuit design engineer saying "Thank God for base current!".

 

Thanks for the core dumps.
Apparently you don't recognize sarcasm. I even added rolled eyes after my question about adding gate current to FETs, to signify such.

To a semiconductor physicist or design engineer, Ib is apparently a useful tool.
I don't think you will ever find a board-level circuit design engineer saying "Thank God for base current!".

Well stated Ron, I do agree with that statement in its entirety. I also wish to add that a board level circuit design engineer is not going to say "thank God for Vbe!" Again, Vbe cannot be removed, so let's deal with it in a manner similar to other parameters, making tradeoffs as needed, depending upon which parameters are more important for the task at hand.

Regarding c-b leakage current, some apps are low temperature & leakage is not that big a deal, so we can optimize for high beta. Likewise for low Vce requirement. If I'm using an EF for driving a FET gate, I use 20V Vce rated parts. I get a nice large beta doing this. Since my Vcc supply is merely 12V, a 20V part works great. I enjoy the low base current of a high beta part w/o fearing Vce punch through.

I overlooked the sarcasm regarding FET gate current, but it didn't hurt to mention that FETs, like their bjt counterparts, also incur tradeoffs during the fabrication process. Ideally, there are usually several parameters we look for in a bjt or FET. We'd like to have all w/o undesirable penalties if we can. But we can't. Thanks.

Claude