I am a student in power electronic filed. When I design PCB and calculate the junction temperature of MOSFET, I am very confused about the thermal design question.

My PCB design is here: (in the middle of the figure) : three MOSFETs in parallel, so 12 MOSFETs(Rthj-c=0.4 from datasheet) in one converter converter by one TIM pad (Rtim=0.62 from datasheet), we have four converter in one cold plate, so 48 MOSFETs on the single cold plate.

I read some documents, it says we should calculate based on single MOSFET like this: (the top in the figure): Pv*(Rthj-c+Rtim+RHA)=Ta-Tj. If we just have one mosfet I agree with it. But actually we have 48 MOSFETs and 4 Tims! So in my opinion, I should calculate in the bottom of the figure. I think the Rthj-c should be reduced because we have 48 Rthj-c to parallel, Rtim should be also changed because the contact area will be smaller than TIM aera. But that's so complicated, and the results looks wrong, RHA will be a negative value!

I am so confused about this. I am working in a project, my colleages calculate them based on single MOSFET, becuase they said it is independent. But I am thinking we do have 48 MOSFETs, could we use Rthj-c=0.4? and the contact aera of TIMpad is small, could we use Rtim=0.62?

I would appreciate it if someone could help me! Thanks so much!

 

Dear Circleplus7,

I'm about as confused as you!
But let's bring some light into this. First you need to find out what that Rtim=0.62 from the datasheet means. I suspect it is the thermal resistance of the material proper, typically expressed for one meter. Imagine a cube of 1x1x1m of that material. You apply a heat source, evenly distributed over one surface of that cube, and cool it on the opposing surface, also all across it. The temperature difference that will appear between the sides, for every watt of thermal power flowing through that cube, would be 0.62°C.

But check the datasheet to make sure that this is really what's meant!

So, to get the actual thermal resistance of the little thing layer of this material between your transistor and the cold plate, you need to adjust this 0.62 number according to the much smaller thickness (which is good!), but also according to the much smaller area of the transistor. Only the actual metal surface of the transistor counts, since the plastic conducts very little heat.

So, for example, if the layer is 0.0003m thick, one square meter of that material would have a thermal resistance of 0.000186 °C/W. But your transistor might only have 0.0001m² of metal surface, and so the thermal resistance of the interface layer goes up to 1.86 °C/W! Check the actual values dimensions, and calculate the correct value.

Then you can add this interface layer thermal resistance directly to the junction-to-case thermal resistance of the transistor used. This is your total junction-to-heatsink thermal resistance, per transistor.

And now you absolutely need to know the thermal resistance of your hot plate, under the actual operating conditions you will have! If you can't get the value from the manufacturer, then you have to measure it, by applying a heat source evenly over the whole mounting surface of the hot plate, and measuring how much it warms up over the ambient.

Now you can choose whether to calculate per transistor, or for all 48 together. In the first case, you take the total junction-to-heatsink resistance of one transistor, and the thermal resistance for the part of the hot plate corresponding to one transistor. So you need to take a hot-plate-to-ambient thermal resistance 48 times higher than the one claimed by the manufacturer. You add that one to the junction-to-heatsink thermal resistance for one transistor, and that gives you a first approximation the total junction-to-ambient thermal resistance for one transistor. You can now use the amount of power that each of your transistors will maximally have to dissipate, to calculate how much its junctions will heat up over the ambient. Then add the expected maximum ambient temperature, and you get a first approximation to the expected maximum junction temperature.

If instead you want to calculate for all 48 transistors together, then you take the actual thermal resistance value of the whole cold plate, and you take one transistor's total junction-to-heatsink thermal resistance divided by 48, add that to the hot plate's resistance, and then you calculate the junction temperature using the total dissipated power of all 48 transistors together. The result will be the same, but of course this is valid only if all transistors dissipate the same amount of power.

If this is below 90°C or so, then you can pretty much stop the process here, and build your circuit. And if you get a junction temperature above 120°C or so, it's too hot for reliable long term operation, and you need to find a better solution. And if it's in between, then you need to consider the finer details:

The hot plate's thermal resistance is quoted for a heat source evenly distributed over the entire surface. But you don't have that! Instead you have 48 small heat sources. So there is some additional thermal resistance, caused by the thermal bottleneck that forms under each transistor. There are online calculators to calculate this additional thermal resistance, based on all the dimensions and materials. In any case, the result will be worse than the first approximation. Your junctions will run somewhat hotter.

And then there is one more, and very important thing to consider: Connecting MOSFETs in parallel does NOT evenly distribute the dissipation among them. The steady state current, while the MOSFETs are fully on, will distribute moderately well, if you make very symmetric connections. But of this is a switching circuit, operating at a frequency high enough to incur in significant switching loss, then you need to know that parallel-connected MOSFETs are very bad at sharing the switching load! It's safe to consider that in each group of three parallel MOSFETs, one will take almost all of the switching load of the whole trio. So one of each three transistors will get much hotter than the others. You need to know how much, and calculate the junction temperature for those extra hot MOSFETs, and make sure that these will run cool enough to be reliable!


Taking the numbers on your sheet: 33.9W dissipation per MOSFET, 0.4 °C/W junction to case, and assuming the 1.86 °C/W of thermal interface material thermal resistance, which I calculated for assumed values of material thickness and transistor metal surface, the junctions would be 76.6°C hotter than the cold plate surface is directly under each transistor. Those spots of the hot plate will be a little warmer than the average temperature of its surface, and from that average temperature to the ambient you need to apply the hot plate's rated thermal resistance and the total power (1627W). Then add the highest expected ambient (or cooling medium) temperature. And then, of course, find out whether your 33.9W per transistor is realistic! Surely it is not. With parallel transistors, some will dissipate a lot more than others.

Don't despair. Many designers of electronic equipment get their thermal design wrong, and end up building equipment that's unreliable due to plain old overheating! So take your time and work through it. Get your design right!

Manfred

 

Hi Manfred,

Thanks for your very detailed explaination. You are correct, I should check the exact meaning of Rtim=0.62 from datasheet. I need some time to understand what you are saying.

But one more question. I don't understand why it is necessary to know RHA (the thermal resistance of cold plate). In my experience, we can measure the surface temperature of the cold plate surface ( under the TIM pad and near the hotest MOSFET) . It is 55C. (the initial water glycol temperature is 35C). So we can directly calculate: 55+[33.9W*0.62+0.4)]=90C. per MOSFET, (If 0.62 is correct), we didn't use RHA at all. Because for now we cannot directly test the junction temperature. We have to calculate the junction temperature based on the surface temperature of cold plate. Do you have better advice on that?

Thank you so much!

Jiaqi

 

But one more question. I don't understand why it is necessary to know RHA (the thermal resistance of cold plate). In my experience, we can measure the surface temperature of the cold plate surface ( under the TIM pad and near the hotest MOSFET) . It is 55C.

Hi Jiaqi,

in that case, indeed you don't need to know the thermal resistance of the hot plate, nor the ambient or medium temperature. If you have measured the temperature of the cold plate directly under the hottest MOSFET, and you know how much power that one is dissipating, and you know the thermal resistance of the piece of TIM between the MOSFET and the plate, and of course you also know the junction-to-case thermal resistance, then all this is enough to calculate the junction temperature.

Of course you must make sure that those conditions won't change, to be sure that the junction temperature will stay at the calculated level.

Manfred

 

Hi Manfred

Thank you so much! I agree with you.
I check the datasheet of TIM pad, thermal conduction K=1.6, Thickness t=0.23mm, and The contact area of the MOSFET and TIM pad is 9.9mm*10.1mm. Therefore, the thermal resistance of TIM can be calculated: Rth_TIM=0.23e-3/(1.6*9.9*10.1e-6)=1.44.

However, it is still too high. I learned something new from a website(https://luminusdevices.zendesk.com/hc/en-us/articles/4412008045069-Thermal-How-do-I-pick-a-TIM-). It provides a method called 2D thermal analysis, which assumes that the effective length, L, doubles in each layer so the area increases by a factor of (2L)^2 (detailed explanation and example in that website). Then I can get the new Rth_TIM as Rth(shape_factor_area) = 1.44/4=0.36K/W. It looks like a normal value. But I am not sure if this method is suitable. Do you have any idea about this method?

Best regards
Jiaqi

 

Hi Jiaqi,
yes, for those values of TIM thermal conductivity, and dimensions, a thermal resistance of 1.44 °C/W is correct.

The ultra simplified 2D method provided on that website is extremely crude, and as they say, provides only an order of magnitude estimation, not a precise value. And worse, it's not applicable to your project, because you don't have such a heat spreader between your MOSFETs and the TIM! The example given on that website refers to a LED soldered to a metal-base PCB, and then having some TIM between that PCB and teh heatsink. So it gives a crude estimation of lateral heat spreading inside that PCB's metal base. But you are mounting your MOSFETs directly on the TIM layer and the cold plate, so there is no heat spreading layer.

Therefore, 1.44 is the correct value, assuming that the dimensions you gave for the MOSFET refer to its metal surface. If instead they refer to the entire size of the MOSFET, including some plastic margins, then the actual value of thermal resistance will be even higher!

Manfred

 

Hi Manfred,

Thanks for your patient explanation.
Yes, you are exactly correct. I learned a lot from you.

1.44 is based on the entire surface of the MOSFET case (including the plastic part). For the metal part (heatsink) of the MOSFET case, the contact area is 5.67mm*8.3mm, Rth_TIM=0.23e-3/(1.6*5.67*8.3e-6)=3.05. It is too high! How could we get a lower Rth_tim? I think around 0.5 will be good.

Thank you again!
Jiaqi

 

1.44 is based on the entire surface of the MOSFET case (including the plastic part). For the metal part (heatsink) of the MOSFET case, the contact area is 5.67mm*8.3mm, Rth_TIM=0.23e-3/(1.6*5.67*8.3e-6)=3.05. It is too high! How could we get a lower Rth_tim? I think around 0.5 will be good.

If you need lower thermal resistance, the options are:

- Use better TIM. Perhaps thinner, if the voltage used allows that. Electrically insulating TIMs having a dramatically higher thermal conductivity won't be available. Maybe a little better than what you have.
- Use physically larger transistors.
- Improve the electronic design, so as to reduce power dissipation.
- Use transistors soldered to copper heat spreaders, and mount those spreaders to the cold plate with TIM in between. There you get much larger area for the TIM.
- If possible, consider a design that doesn't need electrical insulation for the transistors, then solder them directly.

Typical solder has thermal conductivity of very roughly 50 times better than insulating TIM. And it can be much thinner!

 

RE:""Connecting MOSFETs in parallel does NOT evenly distribute the dissipation among them.""
Long ago I bought a wonderful welder. Small, damn cheap, and producing sth about 150 Amps. Yet after three days it ended. Opened, inspected. It was half-bridge driven by 3843 where each the upper and lower shoulders was made of 4 pieces parallel 5A MOSFETs. Damn, who is wasting 4 pieces parallel if there ios full World with 20 A, 30 A and 50 A MOSFETs???? Probably the brilliant ever-wise communist China engineers calculated that 4 pieces weak are cheaper than 1 piece good? Anyway, the only cure was to set it on normal transistors.

 

If you need lower thermal resistance, the options are:

- Use better TIM. Perhaps thinner, if the voltage used allows that. Electrically insulating TIMs having a dramatically higher thermal conductivity won't be available. Maybe a little better than what you have.
- Use physically larger transistors.
- Improve the electronic design, so as to reduce power dissipation.
- Use transistors soldered to copper heat spreaders, and mount those spreaders to the cold plate with TIM in between. There you get much larger area for the TIM.
- If possible, consider a design that doesn't need electrical insulation for the transistors, then solder them directly.

Typical solder has thermal conductivity of very roughly 50 times better than insulating TIM. And it can be much thinner!

Hi Manfred,

Thank you so much. Your patient explaination helps a lot!
I will revise our thermal design based on your suggestions.
Thanks a lot.

Best regards

Jiaqi