Thermal pad via design - total finished diameter and hole size?

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SiCEngineer

Joined May 22, 2019
320
Hi,

For best thermal pad design, I used the Cree document https://www.wolfspeed.com/knowledge...al-solutions-for-surface-mount-power-devices/ which suggests 0.3mm diameter vias spaced 1mm apart. In Altium, there are two things that you specify diameter for on a via - the actual hole size and via overall finished diameter.

For a thermal via, should they be set equal, such that the entire via is just a hole? Is there any need at all for the solder pad?

I also see recommendations often that all thermal vias should be capped and filled - meaning insertion of some thermally conductive epoxy and capped for better solderability. Is this always the case, or is it not worthwhile if the power dissipation through the via is low? Is there a power level rule of thumb to follow? Should the thermal pad vias even have solder mask? It seems to be creating short-circuit collisions on my thermal pad, for some reason.

SiC

*image shows a via with 50/50 solder pad/hole and 100% just hole for possible thermal pad via design*
 

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