Whilst I think this will work, I am certain that your expert comments will greatly improve my circuit.

Attached to P7 is a coil of titanium wire with resistance of about 6 Ohms; An ESP32 microcontroller with use PWM to control the amount of energy introduced into the coil to maintain a precise temperature based on feedback from a thermometer.

I hope for expert opinion as to whether this circuit will work.

 

Is there any internal pull ups in the ESP32?
When using a similar circuit with a Picmicro I use a 10k to 5v rather than to GND.
Max.

 

Is there any internal pull ups in the ESP32?
When using a similar circuit with a Picmicro I use a 10k to 5v rather than to GND.
Max.

The ESP32 has software configurable pull-up and pull-down resistors of value about 50k on (most of) its GPIOs

 

Max, wouldn't putting a 10k to +5V pullup on the gate turn the N-Mosfet on all the time, unless the micro sinks the input line low?
Not sure what the default state is of the ESP32 myself?? Usually for a PIC to an IRL type N-Mosfet, I just put in a pull-down on the gate to keep it off unless the PIC turns it on with a high signal. That said, most PICs start off with IO pins as high impedance when powered on, so 10k pulldown is usually a good idea in those cases.
Again, boils down to what state does the ESP32 start with?

 

The pic ports are initially inputs, I configure the outputs first and set them low.
Max.

 

The pic ports are initially inputs, I configure the outputs first and set them low.
Max.

I too setup pins as outputs and set them low initially.

The ESP32 GPIOs offer only 3.3V --- what do you think of the resistor values for PWM at say 10Hz?

 

I would think 7.5k to 10k should be fine.
I have never used that device, however.
Max.

 

"Normally" this interface is pull down to ground. Most (not all, you have to check)
processors these days start up with outputs in tristate or configed as inputs. So a pull
down insures the pin starts up with a logic 0 by absorbing the pin leakage.

The value needed is to insure whatever load is not turned on by leakage. So you
use R <= Vturnon / Ilkeakage, Ileakage the datasheet value when part hot, both
MOSFET and processor leakage need to be used. Obviously R tolerance has to
be accounted for as well.

The other consideration is pulldown wants to not consume much current as it reduces
noise margin when output is on at logic 1. So high value preferred. But equation above
controls the value.

You will also see the pulldown right at gate, after series R into MOSFET gate. That
method creates a V divider which provides less drive to MOSFET, hence results in
higher MOSFET Rdson. In both cases drive is also lost due to V drop across P Channel fet
in output pin structure becuse of current drawn by pulldown. Because the pulldown is fairly
high in any case the method you are using yields more mosfet drive.

One consideration on placement of pulldown is, for example, if there were wire/cable runs
to MOSFET then pulldown at MOSFET gate preferred in case of wire/cable failure. Also in
this case the series R best close to micro, as it will help mitigate the "Q" (inductance) of the
cable/wire run out to MOSFET.


Regards, Dana.