The enable input

Thread Starter

prophoss

Joined Feb 26, 2019
31
I followed along with a verilog tutorial. It was meant to create a mux with 2 inputs with 1 output. For actual inputs we have input(clk, enable, switch_1, switch_2) and 1 output(LED)
So, I figured out the pins for everything but the enable. I will tray and attach the code to look at.
My question is what pin do I set the enable input to?
Also, if anyone can help, I would like to figure out how to create a testbench in quartis2 ver13

module LED_Blinker
(
i_clock,
i_enable,
i_switch_1,
i_switch_2,
o_LED
);

input i_clock;
input i_enable;
input i_switch_1;
input i_switch_2;
output o_LED;

parameter c_CNT_100Hz = 125;
parameter c_CNT_50Hz = 250;
parameter c_CNT_10Hz = 1250;
parameter c_CNT_1Hz = 12500;

reg[31:0] r_CNT_100Hz =0;
reg[31:0] r_CNT_50Hz = 0;
reg[31:0] r_CNT_10Hz =0;
reg[31:0] r_CNT_1Hz =0;

reg r_TOGGLE_100Hz = 1'b0;
reg r_TOGGLE_50Hz = 1'b0;
reg r_TOGGLE_10Hz = 1'b0;
reg r_TOGGLE_1Hz = 1'b0;

reg r_LED_SELECT;
reg w_LED_SELECT;




always @(posedge i_clock)
begin
if (r_CNT_100Hz == r_CNT_100Hz-1)
begin
r_TOGGLE_100Hz <= !r_TOGGLE_100Hz;
r_CNT_100Hz <= 0;
end
else
r_CNT_100Hz <= r_CNT_100Hz +1;
end


always @(posedge i_clock)
begin
if (r_CNT_50Hz == r_CNT_50Hz-1)
begin
r_TOGGLE_50Hz <= !r_TOGGLE_50Hz;
r_CNT_50Hz <= 0;
end
else r_CNT_50Hz <= r_CNT_50Hz +1;
end


always @(posedge i_clock)
begin
if (r_CNT_10Hz == r_CNT_10Hz-1)
begin
r_TOGGLE_10Hz <= !r_TOGGLE_10Hz;
r_CNT_10Hz <= 0;
end
else r_CNT_10Hz <= r_CNT_10Hz +1;
end


always @(posedge i_clock)
begin
if (r_CNT_1Hz == r_CNT_1Hz-1)
begin
r_TOGGLE_1Hz <= !r_TOGGLE_1Hz;
r_CNT_1Hz <= 0;
end
else r_CNT_1Hz <= r_CNT_1Hz +1;
end

always @(*)
begin
case({i_switch_1, i_switch_2})
2'b11: r_LED_SELECT <= r_TOGGLE_1Hz;
2'b11: r_LED_SELECT <= r_TOGGLE_10Hz;
2'b11: r_LED_SELECT <= r_TOGGLE_50Hz;
2'b11: r_LED_SELECT <= r_TOGGLE_100Hz;
endcase
end

assign o_LED = r_LED_SELECT & i_enable;


endmodule
 
Top