Synchronous Counter (16 bits?)

Thread Starter

Salvatore

Joined Mar 9, 2016
6
Hello people of the AAC community (I'm new to the AAC forums, so bear with me).

So, to the point. I am given by a teacher this project:

Create and design a Synchronous Counter that starts from the number 42110 reaches 103110 and restarts (a loop from 421 to 1031).

I have to use one of these ics: 74ls163, 74ls191, 74ls93 (in the quantity that's needed) and a Timer555 in burst mode (astable).

I think that i'll go with 4 ics of 74ls163 (correct me if i'm wrong, regarding the number of ics needed). We want the timer to give pulses every 1-2sec (what are the R and C values to achieve that)?
I would appreciate it if you could help me with the design (schematics, wiring etc).

Thanks in advance,
Salvatore
 

Thread Starter

Salvatore

Joined Mar 9, 2016
6
Don't get me wrong, i don't want anyone to do the hard job for me. As far as i know the design will be based on this logic

Also i know that i must use the proper logic ics to make the counter stop at 1031. What i want from the people of the forum is to give me some answers on what I ask above and to give me any help they are willing to give. That's all. Sorry for the misunderstanding (and also for my mediocre use of the English language).
 

AnalogKid

Joined Aug 1, 2013
8,217
Step 3 - the 555 timing components are indicated in a graph in the datasheet.

Step 2 - Do the start and end count values have any characteristics that make this problem easier?

Step 1 - Why 4 counter chips? How many bits does the entire count cycle span? How many chips to cover this span? Why?

ak
 

hp1729

Joined Nov 23, 2015
2,304
Don't get me wrong, i don't want anyone to do the hard job for me. As far as i know the design will be based on this logic

Also i know that i must use the proper logic ics to make the counter stop at 1031. What i want from the people of the forum is to give me some answers on what I ask above and to give me any help they are willing to give. That's all. Sorry for the misunderstanding (and also for my mediocre use of the English language).
Your counters are PRESETTABLE? Preset to 421 on a count of 1031.
 

Thread Starter

Salvatore

Joined Mar 9, 2016
6
Step 3 - the 555 timing components are indicated in a graph in the datasheet.

Step 2 - Do the start and end count values have any characteristics that make this problem easier?

Step 1 - Why 4 counter chips? How many bits does the entire count cycle span? How many chips to cover this span? Why?

ak
thanks for the help. The preset number is 421 (decimal) and we want to count till i get to 1031 (decimal). Since the counters will count in binary i thought that 4 4bit counters give us 16 bits since 1031 in binary is 0000010000000111
 

hp1729

Joined Nov 23, 2015
2,304
Hello people of the AAC community (I'm new to the AAC forums, so bear with me).

So, to the point. I am given by a teacher this project:

Create and design a Synchronous Counter that starts from the number 42110 reaches 103110 and restarts (a loop from 421 to 1031).

I have to use one of these ics: 74ls163, 74ls191, 74ls93 (in the quantity that's needed) and a Timer555 in burst mode (astable).

I think that i'll go with 4 ics of 74ls163 (correct me if i'm wrong, regarding the number of ics needed). We want the timer to give pulses every 1-2sec (what are the R and C values to achieve that)?
I would appreciate it if you could help me with the design (schematics, wiring etc).

Thanks in advance,
Salvatore
http://www.electronicspoint.com/threads/presettable-counters.277927/

Data sheets will often include basic application examples.
 
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