Hello, I am trying to generate the following switching pattern for a multilevel buck converter. The converter uses 4 top switches, 4 bottom switches, and 4 phases (each phase = 2.5 µs, total switching period = 10 µs). I need each top switch to follow one specific ON–OFF pattern:

• S4: ON from 0–5 µs (Phases 1 and 2), then OFF from 5–10 µs (Phases 3 and 4).
• S3: OFF from 0–2.5 µs (Phase 1), ON from 2.5–7.5 µs (Phases 2 and 3), then OFF again from 7.5–10 µs (Phase 4).
• S2: OFF from 0–5 µs (Phases 1 and 2), ON from 5–10 µs (Phases 3 and 4).
• S1: ON from 0–2.5 µs (Phase 1), OFF from 2.5–7.5 µs (Phases 2 and 3), then ON again from 7.5–10 µs (Phase 4).

How can I implement this type of switching sequence in LTspice?

 

Using your picture:
1) Make a voltage source with 5uS=on, 10uS=period, delay=0.
2) Make the next voltage source the same but with delay=2.5uS.
3) but with delay=5uS.
4) but with delay=7.5uS.

 

Using your picture:
1) Make a voltage source with 5uS=on, 10uS=period, delay=0.
2) Make the next voltage source the same but with delay=2.5uS.
3) but with delay=5uS.
4) but with delay=7.5uS.

Hello,
I believe I have implemented the same timing sequence, but it is not working as expected. I have attached the .asc file, and I would greatly appreciate any modifications or suggestions that would help me achieve the desired switching pattern.

 

You have 10uS period with a delay of 0, 2.5, 5.0, 7.5 Good
I think you want 50/50% on time not 25/75%.
Try changing Ton from 7.5u to 5u.

 

Hello, I am trying to generate the following switching pattern for a multilevel buck converter. The converter uses 4 top switches, 4 bottom switches, and 4 phases (each phase = 2.5 µs, total switching period = 10 µs). I need each top switch to follow one specific ON–OFF pattern:

• S4: ON from 0–5 µs (Phases 1 and 2), then OFF from 5–10 µs (Phases 3 and 4).
• S3: OFF from 0–2.5 µs (Phase 1), ON from 2.5–7.5 µs (Phases 2 and 3), then OFF again from 7.5–10 µs (Phase 4).
• S2: OFF from 0–5 µs (Phases 1 and 2), ON from 5–10 µs (Phases 3 and 4).
• S1: ON from 0–2.5 µs (Phase 1), OFF from 2.5–7.5 µs (Phases 2 and 3), then ON again from 7.5–10 µs (Phase 4).

How can I implement this type of switching sequence in LTspice?View attachment 359807
View attachment 359806

What is the load current and voltage output specs?

Basically, signal S2 is an inversion of S4, and signal S1 is an inversion of S3.
I'm using a (master) CLK signal and digital buffers to produce the mosfet drive waveforms.
A Duty cycle of 50% produces the output shown below.