Sorry, I don't have time to watch videos.

In order to design what you call your servo amplifier, you have to accurately understand the other components of the loop gain. If the servo amplifier is like you have drawn it then you have a Type 2 PLL. There are two integrators in the loop, one is the VCO and the second is the integrator in the servo amplifier. The loop gain is (ideally) infinite at DC and drops at 40dB/decade. You need to figure out where it would be unity so you can place the zero in your servo amplifier to ensure you have adequate phase margin. If you are having trouble with stability then I would suspect that either you don't have sufficient phase margin (probably as your loop gain calculation is incorrect), or the external drift (the tendency of the YIG to change frequency due to say temperature) is too fast for you loop to track. In this case you need to increase the loop bandwidth or reduce the drift.

With no external stimulus the error signal should be zero when the loop is locked, if it non-zero then the loop is tracking a consistent frequency drift. Sounds like you need to understand your YIG stability and the ability of the PLL to track it. If you hold the frequency control line to the YIG constant what happens to the frequency? Is your PLL designed to track it? This is a fairly straightforward control system question you should answer.

 

Hello Tesa23, No the YIG cannot track it.
The amplifier I made only could to improve the error signal pk-pk but the YIG drift is not affected at all.
I have made photos of the resonance at my network analyzer.
I Know that Q- factor of the resonance plays crutial role.
Given this data whatare the functionality properties you think my SERVO PI controller should have?
So I'll try to design it.
Thanks.

sesitivity: 450 KHz/mA
3dB bandwidth 2.2MHz
resistance 2Ohm
inductance 1.5uH

 

My mistake, in the previous post I told you that you had a PLL, I should have re-read my post#3. You in fact have a frequency locked loop, this is because your resonator and circuitry makes a frequency discriminator:



this is easy to see, if Fo is the frequency coming in at A is such that you get zero error voltage at B (the reflected signal from the resonator is in quadrature), then if we set the YIG frequency to Fo+df, then you get a fixed error voltage at B corresponding to the phase difference in the reflected signal from quadrature. If this was a PLL then a frequency error would give you a steadily increasing phase error from the phase detector.

Why don't you replace the YIG with a stable signal generator and make a plot of the error voltage at B as you change the frequency fed into A. This will both give you the discriminator gain at the lock point, as well as showing that your discriminator circuitry is working correctly, If the LNA in the diagram above stays linear then as the reflected signal drops near resonance (about -20dB from your return loss measurement), then the discriminator gain will also drop. Would this be good? Maybe the LNA should be a limiter?

Anyway, once you have checked that the discriminator is working correctly and you measure the error voltage vs frequency characteristic is should be easy to model the control loop.

 

Hello Tesla23 ,I can try and manually make a table of error signal(mixer output)
However I dont understand the follwoing point.
I need to plug this error into a controller which we dont have (we do have some amplifier but its not functioning properly)
How do you reccomend to use the error signal to measure the frequency from the YIG?

another question:
I dont have the ability to change the YIG component,how can I handle its drifting problem when measuring error Vs frequency plot you asked?
Thanks.

 

I would use some stable signal generator instead of the YIG to measure the performance of the discriminator. You seem to have reasonable lab equipment, can you find a signal generator? I mean something like this (or a more modern version):



Then it is just a matter of stepping the input frequency and recording the error voltage.

If you don't have one, is the YIG stable enough if you feed it from a stable voltage source and measure the frequency with a counter? Alternatively, maybe your network analyser can be used as a stable generator - if you set it to a spot frequency to measure S11 say, what comes out of the test port?

The performance of the discriminator part of the circuit is important, if it has a response like the black line here:




then you should probably make sure that the YIG frequency stays in what's labelled the 'useful range' in the figure, otherwise the sign of the gain may change and cause the control loop to push the loop further out of lock. If the response is like my red lines then the circuit should pull toward lock from a large frequency error.

 

Hello Tesla23, I plugged a signal generator into point A of my system(as shown in the diagram and reccorded the error signal voltage which comes out from the mixer(POINT B).The plot below is based on crude manual point writing .At 9518Mhz we have error 0mV , there is a frequency range shown in red arrow where we have crude linear dependancy between frequency and error.
After the red frequency range the error behaves the opposite, exactly in the diagram photo below.
Matlab code is attached.

What steps do I need to do next to know what kind of PID condtroller behavior should i use for locking?
Video of the setup and measurment is attached in the link.

20241222_091558000_iOS.MOV

freq_up=[9516.89,9517.6,9517.69,9517.81,9517.83,9517.86,9517.9,9518,9518.05,9518.07,9518.1,9518.13,9518.18,9518.33,9518.45,9518.68,9519.01,9520.3]
error_up=[40,47,52,31,26,13,3,-0.4,-3.7,-8.3,-13.5,-25,-39,-35,-30,-24,-18,-1]
plot(freq_up,error_up)
xlabel('frequency [MHz]')
ylabel('error signal mixer phase detevtor[mV]')

 

Well done - the frequency discriminator basically works!

The first thing you should check is that you have the sign of the loop gain correct. Note that if the frequency is a bit low, that this produces a positive error voltage. Just convince yourself that the sign of the feedback is such that this will drive the YIG frequency higher. Nothing prevents a loop from locking better than having the gain sign wrong.

Secondly, note that the discriminator gain drops around zero error voltage. This is likely due to either not enough gain on the reflected signal to drive the DBM to saturation - possibly remedied by more LNA gain, or insufficient cancellation of the non-reflected signal. The reflected signal at the cavity resonance is about -20dB, so to accurately measure its phase you probably need about 60dB of directivity - a reasonable challenge. If the discriminator gain drops at the lock point then the loop may hunt. I'd suggest making it possible to set the lock point over a +/- 10mV range so you can move it away from any dead zone. At least you will be able to show that it locks properly.

This measurement gives you the sign and magnitude of the discriminator gain - you need this to design your servo amplifier. Note that the gain is potentially sensitive to the signal amplitude, so you should make sure that you measured the gain with the signal generator set to the same power level as the YIG.

Now for your question as to designing your servo amplifier, well that really depends on what you are trying to achieve. To simply lock the YIG all you need is to arrange feedback and make sure that the loop is stable (remember your control theory). As the YIG has one pole at 2.2MHz, the simplest loop would probably have a dominant pole to roll the gain off below a few hundred kHz. But that may not achieve what you want.

The authors of the paper you quote were trying to get the best phase noise performance, and their servo amplifier had serious gain:



You have to decide what you are trying to do.

 

Hello Tesla23,regardin what you said below.
How can I see the drop in the frequency discriminator ?

Why do you say that the DBM needs to be saturated?
I know the LO power needs to be 10dBm higher than the RF power.
How does the saturation affects the error signal useful range slope ?

Thanks.

"Secondly, note that the discriminator gain drops around zero error voltage. This is likely due to either not enough gain on the reflected signal to drive the DBM to saturation - possibly remedied by more LNA gain, or insufficient cancellation of the non-reflected signal. The reflected signal at the cavity resonance is about -20dB, so to accurately measure its phase you probably need about 60dB of directivity - a reasonable challenge. If the discriminator gain drops at the lock point then the loop may hunt. I'd suggest making it possible to set the lock point over a +/- 10mV range so you can move it away from any dead zone. At least you will be able to show that it locks properly."

 

The discriminator gain drops around 9518MHz:


which is the resonant frequency of the cavity. This is the frequency where the reflected power from the cavity is minimum. My simplistic interpretation was that the reduction in the reflected power would cause the drop if the DBM wasn't saturated.

However, closer analysis of the paper you posted reveals that this simplistic analysis may be flawed. the cavity reflection coefficient is



and the nulling arrangement (A1, phi1) I suspect nulls out the real part at resonance:



and so what goes to the DBM is the imaginary part:



which is proportional to the frequency offset from resonance. This doesn't appear to have a gain reduction at resonance, in fact the gain seems to peak at resonance and drop at the -3dB points.
So I am not sure what is causing the gain drop, just to say that the discriminator is not operating as described in the paper. Maybe it's not nulled correctly, maybe the quadrature phasing is not correct, you should investigate.

 

Hello Tesla23,If I understand correctly we have a range from 9517.89MHz to 9518.17Mhz which is a very narrow -0.28Mhz range where all the locking needs to be performed.
Actually the error plot looks exactly as the resonance phase shape.
SO beyong this range of 9517.89MHz to 9518.17Mhz we cannot get a lock correct?


I am trying to understand how do i set the behavior of the controller (C block in the diagram)from this .
There are two cases:
1.Suppose My controller gets 52mV inputs(9517.89Mhz)
My controller needs to output a current which will reduce the error voltage.
2.My controller gets -39mV Input so the output needs to be a current which will increase the error voltge .

I can produce a table current as a function of frequency in my YIG or other VCO.
I can build a simple controller where I would have voltage input current output characteristics.

When its all dynamic its hard for me to see the behavior.
Is there a way I could see for example case 1?
Where the controller is having 52mV and its "trying" to reduce the error voltage?
How can I see this "trying to reduce " in my system.
Thanks.

 

You should be able to design a control loop to lock the frequency. It is some sort of class project so you should do that. Given the gain drop in the discriminator characteristic, I'd make the set point adjustable onto the steep part of the curve.

I still suspect there is something wrong with the discriminator, if you look at the paper, what comes out of the DBM should be



where is a normalised offset frequency from resonance which equals 1 at the unloaded -3dB point of the cavity. If you plot this





this is similar to your curve, but with no loss of gain at the origin.

 

Hello Tesla23, yes I understand regarding the drop around the resonance point.I'll try to look at the functionality of the mixer.
Regarding the controller for the YIG (VCO):
I have two coils , the first is large tune coil with drifting .
This tune coil I set at close as possible to the resonance frequency.
The second coil isFM coil:
1.5uH inductance and 1Ohm resistance FM coil.
sensitivity 400Khz/mA

We are tuning the error using the FM coil, so the large tune coil is out of the feedback correction picture.
Tune is not something I changethis coil getting all the time the same signal and its drifting.
I need somehow to change the signal in the FM coil so it will compensate for the drift coming from the tune coil.
I know you said that building the controller is a project i need to do on my own I just need general strategy direction.
I learned that maybe I should use PI controller .Is it correct?
Could you please give me general direction regarding such controller?

Thanks.

 

I have not followed this thread closely for a while, but if the main tuning coil is producing some drift, then perhaps it should be included in the control loop. Or possibly be driven by a constant regulated current power supply. Drift by any elements in a control system can certainly be a source of problems, including incorrect operation.

 

You clearly need to either have a loop that tracks the drift (and if it drifts more than the FM coil can track then you need to involve the tune coil), or you need to stop the drift. If the drift is due to temperature changes then presumably some form of temperature stabilisation would help. Are you allowing the YIG to stabilise after power up before you run your test?

You could have a slow control loop tracking the drift and a fast loop to reduce the phase noise. You should discuss this with your supervisor.

As I have asked before, what are you trying to do? If is is simply to achieve some sort of lock then the easiest approach is to track the drift and apply feedback to the tune coil in a low bandwidth control loop. If you are trying to achieve the type of phase noise performance achieved in the paper then you need a very sophisticated controller to achieve the high gains they described, along with the sorts of temperature and vibration stabilisation they used. If necessary you also need to track the drift. If you really are trying to reproduce the phase noise performance in the paper, I'm skeptical of your prototype setup as shown in your pictures.

 

Hello Tesla23,I am not trying to achieve the phase noise performance of the paper.I am trying to get the best locking performance from the given setup.
My current strategy "Trying" to compensate the tune coil drift (without waiting for the tune to stabilize) using the controller which is changing.
as you can see in the spectrume analizer photo this drift is 5MHz totally,each 1mA is 400Khz, so the FM coil needs to be 12mA to handle it which is no problem .
could you please give some tips regarding thedesign properties needed in the PI controller so It would have a "chance" to handle the drift coming from the tune coil?
Thanks.

 

What I see is a system that needs a a separate frequency control system, rather than trying to have one "servo"correct for the wandering of two different variables. Compensating for warmup drift in addition to trying to produce resonance tracking is not likely to succeed.
Back in the second semester of my feedback systems class, it was pointed out that unstable hardware will always make it much more complex to provide stable operation. Certainly the results discussed so far have proven that to be correct.

 

Hello Tesla23,I am not trying to achieve the phase noise performance of the paper.I am trying to get the best locking performance from the given setup.

What is 'best'? You should speak to your supervisor and work out what it is that you are trying to do.

I agree with Bill, with the information we have to date it appears that tracking that drift is a separate task to the fine, fast tracking to improve the phase noise. But you tell us that you are not trying to improve the phase noise, so why not just a simple slow loop to track the drift with feedback to the tune coil? You would need to check that the drift doesn't take it out of the useful range of your discriminator.

 

Hello Tesla23,In the manual below we can see that a PI controller can be used to "improve" the IN so it will resemble the Ref input. In My system we have the error as one input and GND(0V error as the other input).
I have a Tune drift which changing the output error signal gradually(coming from the mixer),
Why cant the PI controller below handle the Drift error ?
Thanks.