Hello, i am trying to implement the circuit shown bellow.its a PLL device.the mixer produses DC voltage signal which is error between the reference oscilator and the main oscilator as described in the attached article.idially the error voltage needs to be zero and the reference frequency needs to match the main oscilator frequency.
basickly the heart of it is the SERVO amplifier.the servo amplifier takes the error voltage and converts it into chaging the reference oscilation of frequency.
looking at the diagram bellow is there a way to predict wether servo amplifyer could achieve the desired locking between the refrence and main oscilators?
Thanks.

 

This is the identical circuit to a recent post, and neither had a "reference oscillator. The effort then was to lock the YIG oscillator to the resonant frequency of the cavity. The plan appears to be based on the cavity having a much more stable frequency. So why not use the cavity itself as the frequency determining element of an oscillator, and then phase lock the YIG oscillator to that? Itwould be less complicated and require fewer adjustments.

 

This can be analyzed the same as a basic phase locked loop. If I take a PLL using a mixer:



the reference oscillator and mixer (in the red border) take the VCO signal at A and returns a signal at B which is the phase difference between the VCO signal and the reference signal.

You should be able to recognize your circuit as replacing the reference / mixer as:



where the VCO signal at A enters, and what returns at B is a signal representing the deviation of the frequency of the VCO from the centre frequency of the resonator. You should design the 'servo amplifier' as you would design a loop filter in a PLL and ensure you have adequate bandwidth to achieve the desired phase noise suppression, and sufficient gain/phase margin for stability. I imagine you will have to account for the (probably) low pass response of the YIG control. You will need to think carefully as to how many integrators there are in the loop as superficially it looks like the error signal depends on the frequency and not the phase. There is plenty of literature on PLL design available.

As this is a school project, you need to make some progress.

 

Hello ,In the diagram below they did do carrier supression with A1 and phi1 but then they amplified the whole signal.
What is the purpose of first nulling the carrier and them to amplify it?
it seems to me like the mixer will compare the YIG signal to amplified white noise and i dont see any logic in that.

 

It appears to me that the goal is to phase lock the YIG ooscillator device with the very stable resonant frequency of the cavity. Thus the motivation is to collect the resonance signal from the cavity and use that as the PLL reference signal. I question the validity of that concept, which is why I suggested using the cavity exclusively as the frequency determining element in an oscillator. But the published article in the link appears to claim that the intended scheme will work. I am not quite so convinced of that.

 

Hello ,In the diagram below they did do carrier supression with A1 and phi1 but then they amplified the whole signal.
What is the purpose of first nulling the carrier and them to amplify it?
it seems to me like the mixer will compare the YIG signal to amplified white noise and i dont see any logic in that.

I answered this back in June when you were last working on the problem:
https://electronics.stackexchange.com/a/669009/276605

 

None have challenged or agreed with my understanding of the intention., and the original referenced technical paper left me wondering. And then, none have commented on my interpretation stated in post #5.
Repeating ones goal in some effort is entirely acceptable in this forum, in fact it is often suggested. Very few have mind-reading abilities such that they can clearly discern what some TS is actually seeking.

 

None have challenged or agreed with my understanding of the intention., and the original referenced technical paper left me wondering. And then, none have commented on my interpretation stated in post #5.
Repeating ones goal in some effort is entirely acceptable in this forum, in fact it is often suggested. Very few have mind-reading abilities such that they can clearly discern what some TS is actually seeking.

I think that there is nothing fundamentally flawed in the approach. The referenced paper does show that the phase of the reflection coefficient from the cavity does vary rapidly with frequency around resonance (not unexpected), and that can be used in a control loop with a VCO to stabilise the VCO frequency. This is novel, I haven't seen it before, a method of disciplining an external oscillator with a high-Q cavity. As to how practical or useful it is, I have no idea.

You could use the cavity as the resonator in an oscillator, but that is not the issue here. I haven't stuidied this in detail (it seems unnecessarily complicated fo the things I do), but an obvious question is does this method load the resonator less, i.e. can you get a higher loaded Q in this setup than when you use the resonator in an oscillator. If so, then on at least one level, this approach may offer some advantage.

 

There is always a trade-off. Higher oscillator circuit gain with looser coupling improves the long-term stability but tends toward greater phase noise, depending on the circuit design and component noise. So it seems that the choice must depend on the application, and probably the project budget.

 

Hello Tesla23,yes i agree that with this method i can null the leakage of the circulator.
However as you can see below in the article they dont only want to kill the leakage from the circulator but also the return signal from the cavity oscillator.

so if we killed all the feedback signal how are we going to compare the YIG with the resonator?
we are just comparing a YIG to a NOISE in the mixer.

" One way to do it is to replace the cavity with a matched load so that (ideally) there is no reflected wave, then adjust the amplitude and phase of the cancellation circuitry to null out the leakage through the circulator."

 

In post #10 I see a reference to a "cavity oscillator", which is rather confusing, given that the circuit drawing shows a cavity with a claimed very high "Q", of 59,000. I have not seen any reference to it as an oscillator able to produce any signal of it's own.

 

UPDATE:
Hello,I have built the sytem with a proportional amplifier.The green PCB As shown below.
The mixer phase detector is getting in LO and RF same frequency with different phase.
Locking is when the phase difference is getting smaller and smaller.
As you can see the error ripples are getting much smaller but the PLL is always going left and not locking.
When I am designing a controller Itest it using a STEP responce , but in real life as you can see in the scope photos I dont have any step responce I see only ripples and DC error signal,How can I know that my controller will work on the DC of the error signalby looking at the step responce?
Thanks.

 

One more thing that might be the source of the problem now pops into my head. I see a DOUBLE BALANCED mixer!!! I DO NOT SEE A phase detector.
A phase detector is not the same as a frequency mixer.
I have NEVER seen a phase locked lop circuit that did not use a component designed specificly to be a phase detector. If a mixer of any kind would function adequately as a phase detector, certainly the designers would use it.
So while the basic equations may be similar, in reality they are quite different.

 

One more thing that might be the source of the problem now pops into my head. I see a DOUBLE BALANCED mixer!!! I DO NOT SEE A phase detector.
A phase detector is not the same as a frequency mixer.
I have NEVER seen a phase locked lop circuit that did not use a component designed specificly to be a phase detector. If a mixer of any kind would function adequately as a phase detector, certainly the designers would use it.
So while the basic equations may be similar, in reality they are quite different.

Mixers are often used as phase detectors, particularly for their very low phase noise. See https://www.rfcafe.com/references/articles/wj-tech-notes/Mixers_phase_detectors.pdf

 

Hello Tesla23, first of all I see the output voltage changes as I change pi2 phase shifter so the mixer is acting as phase detector.
I got the YIG to be tuned to the resonance frequency (diagram below).
The VCO YIG frequency changes as phi2 changes.
As I showed in the photos I got my error signal pk-pk much smaller but there is a constant drift(because of the YIG) in the mean value of the error signal.I was told that PI controller could handle the drift of the mean value f the error signal.
I am starting to expriment with simulations of PI controller as shown below.
My system is analog PLL with some pk-pk value and a mean value drifting as time goes by.

How can I know that my PI controller will do the job keeping the mean value near the resonance?
Is there some LTspice method i could try to see the effect of my PI controller on the mean value of error signal in the PLL?
Thanks.

 

OK, and I am aware of the theory that a mixer can serve as a phase detector, I have not seen one shown in an actual PLL project that was published. And as I look at the application data for the phase detector in a CD4046 I see a whole lot of difference between that and a DBM. In addition, how would a mixer tell the difference of which frequency is greater??

The other thing is that the loop filter for a PLL has a great deal of effect on the stability and the ability to lock. And the calculations for that filter are not trivial at all.

 

A DBM is very similar to the XOR phase detector in the CD4046 (Phase Detector 1 I think). It has no frequency discrimination, so the capture range of the PLL is small.

The more common Phase/Frequency detector that you see in most CMOS PLL Synthesizer ICs is like the CD4046 Phase detector 2. If one input is higher/lower in frequency than the other it drives the VCO in the right direction, giving the PLL a very wide capture range.

In this case, both frequencies are the same as the mixer is mixing the direct signal from the YIG with that reflected from the cavity. The error signal will be zero when they are in quadrature. As the cavity has a very high Q then the phase of the reflection coefficient changes rapidly through resonance, and locking the YIG to a particular phase of the reflection coefficient stabilises the YIG.

Yef, I don't have time to try to debug your setup from a distance. You have been working on it for a long time. If it was me I would have tried to establish that the various parts work in isolation, in particular I would have replaced the cavity with something with an adjustable reflection coefficient, say using a sliding short, so that you could see that the output of the mixer did give you a measure of the reflection coefficient phase. This would also check your gain calculation. Once you have established that then the design of the PLL is straightforward.

As the YIG has a very wide tuning range, you probably need some sort of acquisition circuitry to drive the YIG frequency to be within the pull-in range of the PLL, but I haven't studied this closely.

 

OK, and as the drawing in post #15 shows the feedback system is indeed a servo system,
And the challenge with servo systems is usually with gain and phase shift, and stability margins. And the challenge is almost always to have adequate gain but not excessive gain, and the correct phase margin. And unfortunately gain and phase are always in conflict with accuracy and stability.

 

Hello Tesla23,thank you very much for the responce. It would be great if you could at least give general feedback regarding th way.
What you said is almost exactly what I have done as shown in the vedoes bellow .
When the phase shift is 90 degrees then error is zero.I can reach this point by tuning into the exact resonance and doing phase shift of 90 degrees by tuning the phi 2 phase shifter.

The main issue is the controller .
There is a PI controller I have simulated.
Is there a way I could see its effect on my error signal?
My error signal is suffering from DC drifting over time.
Thanks.


20241215_095809000_iOS.MOV
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20241215_090423000_iOS.MOV
20241215_082307000_iOS.MOV
20241209_125751892_iOS.heic

 

Both the gain and the phase-shift/response time in a PLL feedback loop are rather critical.