Hi there,

This is not a school project, but rather a home project to build a simple 8-bit computer, and am starting with a clock signal driving registers and a simple ALU. The project comes from: eater.net/8bit

But, I'm stuck on something, any help much appreciated!

The basic clock works great. I have a push button that is using a 555 timer to debounce the signal, so that a button push will cause a rising edge of a clock signal which is used to step a downstream "computer" consisting of 2 registers and an ALU doing some basic math. This works great, pushing the button causes the "computer" to step exactly once, releasing the button causes the clock signal to go LO, with no affect on the "computer" as I'd expect. One press/depress, one computer step. Great!

Now, instead of sending the clock output directly downstream to drive the "computer", I am sending it through a logic gate, then to the same downstream computer, and I am seeing bizarre behavior.

First I am sending it through an OR gate (SN74LS32N).

The OR quad-gate IC is connected to Vcc and ground, one input of the OR is the clock_output signal I described above, and the other input is connected via a 1K resistor to ground. I am then using the output of the OR gate to serve as the clock signal that goes to the computer, and I'd expect to see identical behavior as I saw above. However, in this setup, the computer takes a step on the button depress, but, after holding it down for a while, when I release the button and the signal goes low again, the computer takes *another* step (I should not see any step on the button release).

(I also added a 0.1microfarad capacitor across VCC and GND (pins 7 and 14), but, that didn't do anything to help).
So, that's weird thing #1.

Weird thing #2: Instead of sending through an OR gate, I replaced the OR gate with an AND gate. One input is the clock_output signal described initially, and the other input is now a 1K resistor tied to +5V. Now, when I use the output of AND to drive a clock, holding the button down causes rapid fire mode, as if I was pressing/depressing really really fast. The computer takes multiple steps, more the longer I hold down the button (like automatic fire mode). This AND gate IC also has a 0.1microFarad capactor across Vcc and GND as well, but it doesn't help.

Even stranger, pin 14 (Vcc_in) is connected to power of course (+5V) on the AND chip. However, if I *disconnect* that pin everything works fine, single press of the button through the AND gate, output of the AND gate drives exactly one step of the computer, and nothing on button release, just as it should work. I tried the same thing with the OR chip, there, disconnecting power causes the OR gate to do nothing (as I'd expect) multiple button presses have no effect.

I would expect the computer to respond identically to the debounced button clock signal, whether it's connected directly to the signal, through an OR gate (ORed with Gnd), or through and AND gate (ANDed with +5V). It's also bizarre to me that disconnecting power to the AND IC seems to help, not cause the chip to go dead.

I apologize if this is a totally obvious question. I'm a software guy by training and career, just playing around building an 8-bit computer at home for fun, to learn more about real HW, and to show my kids. I suppose a good next step would be to look at the signals with an oscilloscope, but, I don't have one.

So, I'm at a loss. suggestions much appreciated! (FWIW, I have swapped out different OR and AND gates and still see the same issue, so, I don't think it's a fried chip).

Let me know if any other information would be helpful, or even if anyone is willing to chat about this. Thank you so much in advance for any help!

-Alex

P.S. The clock I've built is the one described by Ben Eater's 8-bit computer project in the 4 youtube videos below. The reason I want to send a clock signal through logic gates is eventually I'm going to have an automatic astable pulse and a monostable push-button driven pulse, and I'll use another switch to select which clock mode goes to the computer. That way the computer can run in automatic pulse mode, or manual push button debug mode. I'm building the setup described in these 4 videos below. (And I've assembled the downstream ALU and registers described in subsequent videos, which is how I'm observing the wonky behavior above from the clock signal effects).

Part 1:

Part 2:

Part 3:

Part 4:

 

Hi,

Wow so retro, 1975ish for me, when i was part of a team that had to do a design for such a system that was to go in to an automated bottling machine. The CPU was one whole PC card all by itself. I had also built my own 8 bit computers at home once i got a hold of some early 8 bit CPU's from Intel, but before that it was all raw logic chips.

The problem seems a little obvious although the exact cause may be hard to figure out. There is something different about the gates you use that cause the problem. What you could try is using a lower value resistor or go to a Schmitt trigger gate.

Did you specify the logic family? Without doing that we dont really know the proper resistor values for everything. 1k pulldown is not good enough for the regular TTL family logic for example.

 

Also the input pins of the unused gates in the chip should be grounded.

 

1kΩ pulldown is not enough for TTL gates. You need 200Ω or lower.

If you are just experimenting with the effects of different 2-input logic gates, connect both inputs together or connect the unused input of OR-gates LOW and unused inputs of AND-gates HIGH.

 

And the downstream input consists of...?

 

Thanks for all the info! Sadly it didn't quite work.

I tied all 7 unused AND chip inputs together (both inputs from the 3 unused AND gates on the chip, and the one input that's on the gate that's also accepting the inbound clock signal). I then connected them to +5V, via 2 220 Ohm resistors in parallel (I didn't have a single resistor < 200 Ohms).

The chips are TTL chips (7400 series), specifically the AND gate is SN74LS08N, the OR is SN74LS32N.

However, behavior is still the same as described about, rapid fire downstream clocks on a button press, instead of just one. As a sanity check if I connect the 2 resistors to ground, I get no clock output as I'd expect, as the AND output is never high. (I haven't tried anything new with the OR chip yet, since that was just a debug step, the final circuit will send this signal through an AND gate).

And, still oddly, if I disconnect Vcc from pin V14 (AND chip power pin), things work (mostly) fine. One press, one clock step downstream (occasionally I see 2 steps on a single button press & release, but only rarely, not sure why that is).

I'm baffled. Any other thoughts? Thanks so much to those of you who put the time in to reply, I really appreciate it! This project is really cool but this one bug is driving me crazy!

atferrari: Downstream the clock signal is being used as the clock input to a 74LS173 4-bit D-type register. I omitted details here b/c it works. That is, if I drive it directly from my debounced push button (via the output of the 555 timer I'm using to debounce), everything is great. It's only when I send that signal first through an AND gate (with the other input of AND high), and use the output of the AND as the input into the register, that I get crazy behavior. The register acts as if it's getting multiple high-frequency clock signals in a row, unlike just one per button push.

 

Schmitt trigger then, as suggested somewhere before.

 

All the replies got me to thinking, and, in retrospect I omitted a critical detail that was the problem! So thank you all for the help.

I looked at the output of the 555 timer (the debounced push button signal which is my clock input to the AND gate that is causing trouble).

That line runs from the 555 timer to the AND gate input of course, but also (b/c I had it there for debugging and never took it out) has a LED hanging off of it, that runs through a 1k resistor to ground.

If I pull those out (the purple bracket LED and resistor in the attached schematic) all works fine!

So, can someone help me understand why this is happening? My guess is that the power/current being pulled off the line through the LED/resistor to ground has the effect of lowering the voltage of the line, so that when it gets to the AND gate, it oscillating right around a voltage low enough that the AND gate thinks it sees high frequency on/off logic signals. The reason it works when the 555 output goes directly to the clock signal on the register is b/c the register has a different threshold / behavior when it comes to determining what voltage is ON or OFF.

Does that sound right?

Schematic attached! And thanks again everyone for the help!

 

You're on the right track.

Never take a logic signal off an output that is already driving an LED (unless you can verify that the logic level is legitimate).

Live and learn.

(Your concept of pull-up and pull-down resistors need revision. In TTL circuits the values are not usually the same. For pull-up, you can use 200-5kΩ depending on what you are driving. For pull-down you need something lower than 250Ω depending on what is driving the input.)

 

I think you are correct.
The 555 high output is less than 5V to begin with, and adding the LED load would lower it even further, so that the voltage could be marginally high for the logic gate input.