I over thought. Reversed the complete chain. Capacitor to VCC and Resistor to Gnd.

 

I over thought. Reversed the complete chain. Capacitor to VCC and Resistor to Gnd.

It can be done that way, but you have need to reverse DISCHARGE as well! But discharge is just an open-collector version of OUTPUT, so a diode from OUTPUT does the trick, and it‘s a handy way to make a circuit with mark-space varying from 0 to 50%.

 

I over thought. Reversed the complete chain. Capacitor to VCC and Resistor to Gnd.

Reverse which resistor?

 

It can be done that way, but you have need to reverse DISCHARGE as well!

No, you don't.

For the basic astable circuit, the voltage at the resistor/capacitor node will behave identically no matter what DC potential the other end of the cap is connected to (as long as that node has a very low source impedance). In one half-cycle, the Discharge pin will pull the node voltage toward GND through one resistor; in the other half-cycle, the node voltage will increase toward Vcc through two resistors. Same parts doing the same things.

The DC potential of the other end of the cap does not change anything about the circuit's operation (after the first half-cycle). As above, the first half-cycle will not be the period calculated by the standard equation, but it isn't in any other 555 circuit either.

ak

 

I just realized that the capacitor would be acting kind of like a decoupling capacitor? But instead of connecting the other lead to GND, I would be connecting it to threshold. I was using already a 1uF and a 100nF capacitors (both between VCC and GND). As discharge capacitor I am using 4.7uF, would this affect a proper work of the 555? Maybe I am just overthinking it

I am using standard version of the 555, not the CMOS

 

I just realized that the capacitor would be acting kind of like a decoupling capacitor? But instead of connecting the other lead to GND, I would be connecting it to threshold. I was using already a 1uF and a 100nF capacitors (both between VCC and GND). As discharge capacitor I am using 4.7uF, would this affect a proper work of the 555? Maybe I am just overthinking it

I'm not picking on you, but this post is a perfect example of why reference designators were invented. I've re-read it several times, and I still have no idea of which caps are connected where.

ak

 

No, you don't.

For the basic astable circuit, the voltage at the resistor/capacitor node will behave identically no matter what DC potential the other end of the cap is connected to (as long as that node has a very low source impedance). In one half-cycle, the Discharge pin will pull the node voltage toward GND through one resistor; in the other half-cycle, the node voltage will increase toward Vcc through two resistors. Same parts doing the same things.

The DC potential of the other end of the cap does not change anything about the circuit's operation (after the first half-cycle). As above, the first half-cycle will not be the period calculated by the standard equation, but it isn't in any other 555 circuit either.

ak

Oh yes you do! If Ramussons "Reversed the complete chain. Capacitor to VCC and Resistor to Gnd." there are only current paths to make the capacitor voltage more negative, there are no current paths to make the capacitor voltage more positive unless DISCHARGE does that.

 

there are no current paths to make the capacitor voltage more positive

Sure there is. In a classic 555 astable circuit, there are two resistors in series between the "top" of the timing capacitor and Vcc. electron flow through these resistors raises the capacitor terminal voltage.

If we all agree on that, then what happens of the "bottom" of the capacitor is disconnected from GND and connected to Vcc?

First, some housekeeping. If it is an electrolytic cap, the part must be reversed such that the anode is connected to Vcc and the cathode is connected to the timing node (pins 2 and 2 for an 8-pin part). This change is not necessary for a ceramic or other non-polarized cap.

Second, don't confuse how we talk about current directions in a circuit with what is important - that things change. When we talk about a capacitor "charging up", we usually envision one end of a cap connected to GND and the other end connected to a positive voltage source through an impedance; one or two resistors in a 555 circuit. Over time, the charge stored in the capacitor increases, and the voltage across the capacitor increases as it approaches the value of Vcc.

BUT

What if one end of the cap is connected to Vcc and the other is connected to GND through resistor(s)? As the charge in the capacitor increases, the R-C node voltage decreaases from Vcc, moving down toward GND with *increasing* charge. There is no standard term for this. Is the cap "charging down"? It is not discharging, because the stored charge is in fact increasing. In fact, the cap is charging up and its terminal voltage is increasing, just like before. The only difference is which end of the cap is being used as the reference for the measurement. And the only thing a 555 sees is a node voltage that ramps exponentially up and down based on the direction of electron flow.

Here's an extreme case: a standard 555 astable circuit powered by 6 Vdc. This sets the Trigger voltage at 2.0 V and the Threshold voltage at 4.0 V. Now, disconnect the bottom of the timing cap from GND, and connect it to a pure DC voltage source of exactly 3.0 V. In a standard 555 circuit, the timing cap charges up through Ra and Rb, and discharges through Rb only. We join the circuit at the moment the timing node (pin 2, pin 6, Rb, and C) voltage dips below 2.0 V. At this time there is 1.0 V across the timing capacitor C: the timing node is at 2.0 V and the other end of the cap is fixed at 3.0 V. The internal flipflop changes state, the Discharge transistor turns off, and C starts charging through (Ra + Rb) from 2.0 V moving toward 6 V. Remember, the other end of the cap is held at 3.0 V, so for a while the cap is discharging as its terminal voltage decreases from 1.0 V down to 0 V. At 0 V nothing magical happens and the cap now starts charging up in the opposite polarity as the timing node continues its ramp upwards toward 6 V. At 4.0 V the threshold input comparators flips the internal flipflop, the discharge pin transistor saturates, and the cap begins to discharge through Rb. Measured from GND, the cap voltage goes from 4.0 V to 2.0 V, but the terminal voltage across the cap goes from +1.0 V to -1.0 V. How we measure the voltage does not affect in any way the amount and movement of charge in/out of the capacitor.

ak

 

Sure there is. In a classic 555 astable circuit, there are two resistors in series between the "top" of the timing capacitor and Vcc. electron flow through these resistors raises the capacitor terminal voltage.
If we all agree on that, then what happens of the "bottom" of the capacitor is disconnected from GND and connected to Vcc?

No we don't agree.
Ramussons "reversed the complete chain. Capacitor to VCC and Resistor to Gnd."
NOW THERE IS NO RESISTOR to V+.

 

Just a moment ... Just a moment ...

I have been discussing the TS circuit in posts 1 and 9 and his proposed change. What he wants to do will work just fine.

Ram did not give a very complete description of the circuit changes in post #21, but if he means what I think you think he means, then no, that will not work.

ak

 

I imagined it this way.

 

hi,
LTSpice, sim.
Two plots with Ctiming to 0V and +v
E

 

@ericgibbs That set of measurements I can not get to fit.

Can you include the two TRIG/THRS signal tracks in the plot?

 

hi,
LTSpice, sim.
Two plots with Ctiming to 0V and +v
E

It‘s a simulation. In real life O0 will immediately go to V+, because TRIG will start below (control voltage)/2, which will SET the output flip flop.

 

I imagined it this way.
View attachment 219747

Yes, and as we all said, it won’t work because there is no path to INCREASE the voltage at C1/R2, BUT if the connection to DIS is removed and replaced by a diode to OUT (anode to OUT, athode to R1/R2) It does work because it makes a positive-going version of DIS, and is a useful circuit, because the mark space varies from 0-50% instead of from 50% to 100%

 

hi Kj,
Is this what you are asking.?
Note: On this sim I have started the sim with the initial Vsup at zero volts, so that you can see the direction of the Vcap charge,
Ask if you want more info.

E

Update:
Note: o1 and o2 relationship.

 

Yes, and as we all said, it won’t work because there is no path to INCREASE the voltage at C1/R2, BUT if the connection to DIS is removed and replaced by a diode to OUT (anode to OUT, athode to R1/R2) It does work because it makes a positive-going version of DIS, and is a useful circuit, because the mark space varies from 0-50% instead of from 50% to 100%

And what’s better about doing it this way? It’s just adding an extra connection and an extra part, even if it could work the path of the resistor to GND then

 

Update:
Note: o1 and o2 relationship.

In the new set of plots show that o1 and o2 start opposite when the time capacitor is connected + V or GND, exactly as I expected.

Has anything changed in start-up conditions in the two simulations?

 

hi Kj,
I normally use LTS with Vsupply starting at the actual Vcc of the circuit.

For a more complete simulation I started the 2nd sim with the Vsup at zero [ as it would be in a practical circuit] ,

This image shows some of the start up options, also most times I skip the initial operating point solution.

E

 

Hi Eric
Thank you for your answers.