Hi all,

In general, Shall we connect the transceiver pins to SPI as shown below?.

SPI_MISO to RXD_P (and RXD_N to GND), and SPI_MOSI to TXD_P (and TXD_N to GND).

 

SPI is a serial peripheral interface which is a 3 or 4 wire (MISO, MOSI, CLK and CS) system to transfer data between ICs.
SCI is an serial communications interface to send data via a RS232/RS423/RS485 interface.
Don’t connect them together at all because it won’t work.

 

SPI is a serial peripheral interface which is a 3 or 4 wire (MISO, MOSI, CLK and CS) system to transfer data between ICs.
SCI is an serial communications interface to send data via a RS232/RS423/RS485 interface.
Don’t connect them together at all because it won’t work.

Yes, I knew that, to communicate over SPI, it's required 4 wire (as you said above). And, to communicate over SCI, it's also required 4 wires. I think I'm correct.
But, Maximum how many slave devices shall we connect on one SPI bus?.

 

SPI doesn't use addressing. Instead each slave has a pin to select it. It will be labeled CS for chip select or SS for slave select these are the same thing. The limiting factors for number of slaves are: the number of available GPIO pins on the master, since in the simplest configuration you must have one free pin for each slave, and; the capacitive loading of the SPI bus since all slaves will have CLK, MISO and MOSI in parallel.

The first limit can be managed by using something like a decoder (e.g.: the SN74LS42 which will use 4 pins to select one of 10 slaves). The second is probably not something you will practically encounter. If you do, you may have the wrong design.

 

. And, to communicate over SCI, it's also required 4 wires. I think I'm correct.

Only 2, RXD and TXD, or one if it is only simplex (one direction only)

But, Maximum how many slave devices shall we connect on one SPI bus?.

until you run out of CS pins. Most microcontrollers (that I have used) seem to have four, but you could add more with GPIO pins.

 

Hi Yaakov and Lan0,

Let take an example:

If I have 20 free IO pins are left on micro controller side, then, shall I connect 20 slaves on a single SPI (MISO, MOSI, SCLK, SS_1 .... SS_20)?.

 

As long as you dont load the bus too much you could. This would ba a very unusual way to do things.

 

I parallel my SPI devices and choose the particular device with an I/O pin to the SS (slave select) or CS (chip select) pin.

 

Hi Yaakov and Lan0,

Let take an example:

If I have 20 free IO pins are left on micro controller side, then, shall I connect 20 slaves on a single SPI (MISO, MOSI, SCLK, SS_1 .... SS_20)?.

On a LPC15xx microcontroller you can select more than one CS (out of the four) simultaneously, so you could expand them with 74HC154 to get 16, but don’t forget that the SPI pins are standard microcontroller outputs with limited drive current that might not cope well with all that capacitance especially at high frequencies. You could buffer MOSI and CLK with a 74AC device with a bit more drive.

 

As long as you dont load the bus too much you could. This would ba a very unusual way to do things.

OK ok..

Lets, If the communication target speed is 100khz, then how many maximum slave devices shall be connected?. I have a many IO free pins are left this case.

 

OK ok..

Lets, If the communication target speed is 100khz, then how many maximum slave devices shall be connected?. I have a many IO free pins are left this case.

Calculate the total capacitance - look in the datasheets for input capacitance. Allow some extra for track capacitances. Assume an output resistance of about 60 ohms. Calculate the time constant, and make sure it is less than 5% of the clock period.

 

Calculate the total capacitance - look in the datasheets for input capacitance. Allow some extra for track capacitances. Assume an output resistance of about 60 ohms. Calculate the time constant, and make sure it is less than 5% of the clock period.

OK.
Can you share the formula for that?.

 

OK.
Can you share the formula for that?.

It’s just R x C.

 

It’s just R x C.

Ok..
But, the input capacitance of what?. In my case, SPI communication between ADC and MCU, DAC and MCU. So which datasheet I have look in to it for the input capacitance.

And also, the output resistance of what?. Is it Load resistance or the output capacitance of either ADC or DAC or MCU?.

Please can you give me the clarity?.

 

https://ww1.microchip.com/downloads...-Bus-Serial-EEPROM-Data Sheet_DS20002123G.pdf
is an example of a SPI peripheral

Page 2 of the datasheet.
Low-level output voltage: 0.4V @ 2.1mA = 190Ω

Further down the same page
Internal capacitance: 7pF

Assuming all the peripherals would be the same:
20 x 7pF x 190Ω = 26ns
If that is 5% of the clock period then the shortest clock period is 532ns, giving a maximum clock speed of 1.88MHz.

 

Assuming all the peripherals would be the same:
20 x 7pF x 190Ω = 26ns
If that is 5% of the clock period then the shortest clock period is 532ns, giving a maximum clock speed of 1.88MHz.

Hi Ian0,

Where did you get these below values:

Where did you get the value of 20? and value of 532ns?.

Please could you explain?. Other part I understand.

 

7pF - from the datasheet.
20 - the number of devices you said you would attach
532ns - the length of time that 26ns is 5% of.

 

7pF - from the datasheet.
20 - the number of devices you said you would attach
532ns - the length of time that 26ns is 5% of.

"If that is 5% of the clock period then the shortest clock period is 532ns".
Why we need to consider 5%?.
Still, the above sentence is not clear to me.

 

https://ww1.microchip.com/downloads/en/DeviceDoc/25AA02E48-25AA02E64-2K-SPI-Bus-Serial-EEPROM-Data Sheet_DS20002123G.pdf
is an example of a SPI peripheral

Page 2 of the datasheet.
Low-level output voltage: 0.4V @ 2.1mA = 190Ω

Further down the same page
Internal capacitance: 7pF

Assuming all the peripherals would be the same:
20 x 7pF x 190Ω = 26ns
If that is 5% of the clock period then the shortest clock period is 532ns, giving a maximum clock speed of 1.88MHz.

Few more question from this:
In my case, I have been using the SPI between the MCU and ADC and DAC. So in this case, Do I need to consider the parameter of Low-level output voltage and Internal capacitance from the ADC and DAC to calculate the target SPI speed of 100Khz?. Forget about the 20 device which I said in post #6. My target is how many devices can I connect with the SPI speed of 100Khz.
Why would we consider low-level output voltage?. why not high-level output voltage?. Why not input voltages?.
In the datasheet, if the internal capacitance is not given then can we consider input capacitance instead internal?.

 

Few more question from this:
In my case, I have been using the SPI between the MCU and ADC and DAC. So in this case, Do I need to consider the parameter of Low-level output voltage and Internal capacitance from the ADC and DAC to calculate the target SPI speed of 100Khz?. Forget about the 20 device which I said in post #6. My target is how many devices can I connect with the SPI speed of 100Khz.
Why would we consider low-level output voltage?. why not high-level output voltage?. Why not input voltages?.
In the datasheet, if the internal capacitance is not given then can we consider input capacitance instead internal?.

Low level output voltage is used to get an estimate of output resistance by dividing by the current at which the low-level output voltage is measured.
You could just as easily use high level output voltage. They should be about the same, but if they are not use whichever is higher.
At 100kHz, you should aim for a time constant below 500ns, that would give rise and fall times of about 1.5us, which is just about good enough to guarantee that it would work. 200ns would be better.
Input capacitance would be the preferred parameter. Not quite sure what “internal capacitance” means, but suspect that they are the same thing.