SN74LS92 frequency divider

Thread Starter

Sebastian-Richard Ene

Joined Oct 9, 2018
Hello, I have a question. How can I use the SN74LS92 IC to design a frequency divider with value 11 ?
I know it has a 12 frequency divider but how can I make it divide by 11 ?


Joined Oct 2, 2009
74LS92 is actually two stages in one.
One stage is a divide by 2 counter. The other is divide by 6.
You only need to decode Q2 and Q3 into an AND gate followed by a flip-flop if you want to delay the reset function to the next clock pulse.


Joined Mar 10, 2018
There is a problem with the reset approach. If you want
it to divide by n then the approach where you decode n
(it counts 0 to n-1) means that it counts 0 to n-1 "normal"
then when its outputs flip to next value, n, it then executes
reset. But notice it had to go to n to do it, although it stays
in this state only a short period of time. So looks like a
glitch on the outputs.

Additionally when you execute the reset the decode output
in just a few nS goes away, which may violate the reset pin
hold time.

This is a problem in asynchronous systems where the above
produces some in determinate timing and can violate chip
timing. one approach is to use synchronous counters.

Regards, Dana.