Say I have two processes to choose for my analog IC, 180nm and 130nm. Those two numbers describe the length of the gate, but the minimum PG grid size is usually way smaller, on the order of tens of nanometers. So what's stopping the 180nm process from being the 130nm process if you could theoretically print a photo mask that had a 130nm length? Also, does the doping and other characteristics change between processes, or just the gate length?

Also, how does gate oxide thickness correlate to process technology? Is it proportional?

Thanks!

 

We're talking about 20 year old process technology at 130nm. Yes, there are more changes than just litho with a 130nm shrink because there are usually other process improvements thrown in to make it worth the money, time and effort to qualify a line.
http://www.chip-architect.org/news/2000_11_07_process_130_nm.html

 

So what are the extra process improvements that are thrown in? I guess my question is, what makes the smaller minimum gate length better, why can't you add those extra process improvements to the bigger gate length technology as well?

 

So what are the extra process improvements that are thrown in? I guess my question is, what makes the smaller minimum gate length better, why can't you add those extra process improvements to the bigger gate length technology as well?

There are 'stepping' improvements without shrinks but in general shrinks are a very good time to roll in improvements.

It's all about making more money and marketing too.
The cost of each wafer remains much the same but with a large increase in the number of die per wafer. $$$
Newer, 'better' products with advanced technology for marketing brochures. $$$

Wafers get bigger while die lines get smaller.

 

So what's stopping the 180nm process from being the 130nm process if you could theoretically print a photo mask that had a 130nm length?

The decisions made when moving from 250nm to 180nm are a matter of priorities. Intel chose to make the area shrink by about 50% between process generations.

250nm * 0.7 = 175nm. Some features can shrink more and some can shrink less, but the overall area reduction target is 50% (0.7*0.7 = 0.49).

Also, does the doping and other characteristics change between processes, or just the gate length?

Anything can change. Doping, materials, inter-layer dielectric thickness, contact/via size, metal width/thickness, etc.

Also, how does gate oxide thickness correlate to process technology? Is it proportional?

It scaled to meet device performance targets. They reached the point where gate oxide thickness can't be reduced several generations ago.